Clock & reset system
RM0082
206/844
Doc ID 018672 Rev 1
With X Y/2, if the post divider is enabled (synt_clkout_sel field is cleared); while
With X Y/2, if post divider is disable (synt_clkout_sel field is set).
Clock synthesizer is based on Y-modulo counter incremented by X. After reset the counter
value is zero and it increments of X every input clock cycle. If N is the number of input clock
cycle the output is high when:
The counter loads the value Y-NX a clock cycle after that it is verified the previous condition,
the output become low and the process iterates again. If Y is a multiple of X
is a constant and the output period is
The output frequency is given by formula.
When Y/X is not an integer value the output period swings between N and N+1 times the
input clock period, with N the integer part of Y/X.
This means that the maximum period drift is of one input clock period.
E.g:
With Fout= 40 MHz, Fin= 333 MHz the synthesizer parameters using are:
X=40 and Y=333
This means that the output clock period is on average: Tout = 8.325 * Tin.
The output period will be 8 or 9 times the input clock period:
Tout = 8 * 3 = 24 ns and Tout = 9 * 3 = 27 ns
The maximum output period drift is 27-25 =2 ns.
Since the output clock is high for one input clock cycle the duty cycle is:
If the post divider by two is enabled the D.C. is 50%; in this case the output frequency is
given by.
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1
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Y
X
Fin
F
out
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Y
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Fin
F
out
2
Y
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N
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Y
N
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X
Y
T
N
T
T
in
in
out
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=
100
(%)
⋅
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Y
X
DC
