RM0082
BS_DMA controller
Doc ID 018672 Rev 1
333/844
19 BS_DMA
controller
19.1 Overview
Within its basic subsystem, SPEAr300 provides an DMA controller (DMAC) able to service
up to 8 independent DMA channels for sequential data transfers between single source and
destination (i.e., memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral).
Main features of the DMAC are:
●
Each DMA channel can support a unidirectional transfer, with internal 16-words FIFO
per channel.
●
16 peripheral DMA request lines, where each peripheral connected to the DMAC can
assert either a single DMA request or a Burst DMA request (with programmable size to
increase data transfer effectiveness).
●
Hardware priority (0 the highest to 7 the lowest) for each DMA channel to manage
requests from more than 1 channel at the same time.
●
Scatter or gather DMA support through the use of linked lists.
●
An AHB slave acting as programming interface to access to DMA control registers:
●
Two AHB masters for data transfer following a DMA request.
●
32 bit AHB master bus width, supporting 8, 16, and 32 bit wide transactions.
●
Support both big-endian and little-endian (Little endian default on DMAC reset).
●
Separate and combined DMA error and DMA count interrupt requests, with three
interrupt request signals (DMACINTTC, DMACINTERR and DMACINTR).
●
Interrupt masking and raw interrupt status (prior to masking).
