RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
107/844
DDR_nDQS_(1:0)
Bidir.
Differential memory data strobe negative line. Drove during
write transaction and received from memory device during
read transfer.
DDR_CLKEN
Out
Memory clock enable (active high)
DDR_CS_(1:0)
Out
Memory chip select (active low)
DDR_RAS
Out
Memory row address select
DDR_CAS
Out
Memory column address select
DDR_WE
Out
Memory write enable
DDR_ADD_(14:0)
Out
Memory address bus
DDR_BA_(2:0)
Out
Memory bank address
DDR_DM_(1:0)
Out
Memory data mask (active high)
DDR_DATA_(15:0)
Bidir.
Memory data bus
DDR_ODT_(1:0)
Out
Memory On-die termination enable signals (active high)
DDR_GATE_(1:0)
Bidir.
Memory gate open (DQS delay tune considering board
propagation delay and internal pad propagation delay)
Table 54.
Internal signals
Signal name
Description
AHB-CFG
Through this bus, connected to the multilayer interconnection matrix output port
#3, the CPU or any other logic block with master capability can configure the
memory controller registers.
AHB0
Through this bus the CPU can access the external memory.
AHB1
Through this bus the master port L can access the external memory.
AHB2
This bus, through the multilayer interconnection matrix output port 5, give access
to the external memory to the following masters:
DMA1
Master port H
AHB3
This bus, thanks to an external multiplexer, give access to the external memory to
the following masters:
DMA2
Ethernet controller
Master port E
Channel controller coprocessor (C3)
AHB4
This bus, thanks to an external multiplexer, give access to the external memory to
the following masters:
USB2 host and device controllers
Channel controller coprocessor (C3)
IRQ
The memory controller interrupt request line is connected to the physical request
number 13
Table 53.
External memory Interface signals (continued)
Signal name
Direction
Description
