DDR memory controller (MPMC)
RM0082
114/844
Doc ID 018672 Rev 1
means that an AHB WRAP instruction is divided into two Memory Controller core
transactions, one for the non-wrapped portion of the transaction and one for the wrapped
portion. The starting address determines whether the WRAP transaction will actually wrap
or not. A wrap transaction with an aligned address is equivalent to an INCRx command and
is treated as such by the AHB port.
Figure 9.
WRAPx effective transaction
Full-Size INCR transactions
Since the Memory Controller core bus protocol does not support transactions of an
unspecified length, AHB INCR transactions require special handling by the AHB port logic.
Each AHB port contains a pair of programmable parameters for determining the length of a
command that will be issued to the Memory Controller core when an INCR command is
issued to the AHB port. These parameters are ahbX_wrcnt and ahbX_rdcnt and they hold
the programmed size used for an unspecified length WRITE and a READ command length
in bytes for port X when this type of command is issued to the Memory Controller core.
The value defined in these parameters should be a multiple of the number of bytes in a data
word for the Memory Controller core. If that is not the case, the parameter values will
automatically be truncated to the data word boundary. Clearing these parameters will cause
the port to issue commands of 0 length to the Memory Controller core, which the core
interprets as the pre-configured value of 1024.
The values for the ahbX_wrcnt and ahbX_rdcnt parameters should be chosen carefully and
should be based on the average length of an INCR transaction expected from the AHB
master. If the values are programmed too low, the AHB port must issue a large number of
small Memory Controller core transactions that may fill up the command queue and reduce
system performance. A full queue may also inhibit higher priority requests from meeting
their latency requirements. On the other hand, if the values for the parameters are
programmed too high, then write transactions may force the AHB port to issue masked
WRITE commands (WRITE commands that do not alter the contents of memory) to the
Memory Controller core to complete the transactions. Similarly, for READ transactions,
programming the length too large will cause extraneous data to be gathered, wasting cycles.
An optimal value for the READ and WRITE length is important.
Note:
The values in the ahbX_wrcnt and ahbX_rdcnt parameters should never exceed 1024.
Starting
Address
Wrap
Address
The command wraps at address:
(Starting X)-Modules(Starting Address/X)
Where X is the Wrap Size in WARPx
Starting Address-Modules (Starting Address/X)
Where X is the Wrap Size in WARPx
WRAPx Command
Length = X*ahbX_HSIZE
Transaction #1
Transaction #2
Memory Page Containing Starting Address
