DDR memory controller (MPMC)
RM0082
144/844
Doc ID 018672 Rev 1
10.10
DCC tuning timing
The command and address for the transaction are sent from the memory controller
coincident with the falling edge of the memory controller clock. Since the clock, command,
and address signals will all have roughly the same pad and flight delays to travel to the
memory, the rising edge of the clock at the memory will be centered with the command and
address signals, allowing reliable capture. To ensure proper memory read write sequences
the DDR memory controller contains a delay compensation circuit that, in conjunction with
I/O cell circuitry, can be used to meet the memory target timing requirements. The delay
compensation circuit offers the following features:
1.
Programmable read clock delay specified as a percentage of a clock cycle:
Read transfer path, should also take in account the memory the flight paths. There is a
certain time lag from when the clock is sent from the memory controller to when the data
and DQS signals are received at the memory controller from the memory. Since the DQS
from the memory will be sent coincident with the data, and the data must be captured
reliably, the DQS signal is delayed through the register field dll_dqs_delay_X so that it is
centered in the data valid window (nominally approximately 1/4 cycle).
2.
Programmable write clock and write DQS delays specified as percentages of a
clock cycle:
Write transfer path are control from dqs_out_shift and wr_dqs_shift register parameters
which set the delay for the DQS signal for dll_wr_dqs_slice and for the clk_wr signal,
respectively. These parameters should be programmed such that clk_dqs_out is in phase
with clk and that clk_wr is 1/4 cycle ahead of clk_dqs_out.
3.
Delay compensation circuit re-sync circuitry activated during refresh cycles to
compensate for temperature and voltage drift:
The delay compensation circuitry relies on a master/slave approach. There is a master
delay line which is used to determine how many delay elements constitute a complete cycle.
This count is used, along with the programmable fractional delay settings, to determine the
actual number of delay elements to program into the slave delay lines. The master and slave
delay lines are identical. This approach allows the memory controller to observe a clock and
then delay other signals a fixed percentage of that clock. The DCC logic does not actively
generate clock signals.
The delay parameters are listed in
. The total delay can be determined based on
the following equation, where param is one of the parameters in the table:
delay = #delays in one cycle × (param[6:0]) /128
1.
Separate delay chains for each DQS signal from the DRAM devices.
2.
Support for multiple DQ:DQS ratios
The DQS bus is a bidirectional bus that is driven by the memory controller on writes and the
memory on reads. When neither device is driving the bus, DQS will remain in a high-
Table 73.
Delay parameters
Operation
Parameter
Clock
wr_dqs_shift
Read
dll_dqs_delay_X
Write
dqs_out_shift
