DDR memory controller (MPMC)
RM0082
132/844
Doc ID 018672 Rev 1
10.6
Core command queue with placement logic
The Memory Controller core contains a command queue that accepts commands from the
Arbiter. This command queue uses a placement algorithm to determine the order in which
commands will be executed in the Memory Controller core. The placement logic follows
many rules to determine where new commands should be inserted into the queue, relative
to the contents of the command queue at the time.
Placement is determined by considering address collisions, source collisions, data
collisions, command types and priorities. In addition, the placement logic attempts to
maximize efficiency of the Memory Controller core through command grouping and bank
splitting. Once placed into the command queue, the relative order of commands is constant.
Many of the rules used in placement may be individually enabled/disabled. In addition, the
queue may be programmed by the placement_en parameter to disable the placement logic
entirely, resulting in an in-line queue that attends requests in the order they are received. If
the placement_en parameter is cleared to 1'b0, the placement algorithm will be ignored.
10.6.1
Rules of the placement algorithm
The factors affecting command placement together work to identify where a new command
fits into the execution order. They are listed in order of importance.
Address collision/Data coherency violation
The order in which READ and WRITE commands are processed inside Memory Controller
is critical to proper system behavior. While READs and WRITEs to different addresses are
independent and may be re-ordered without affecting system performance, READs and
WRITEs that access the same address are significantly related. If the port requests a READ
after a WRITE to the same address, then repositioning the READ before the WRITE would
return the original data, not the changed data. Similarly, if the READ was requested ahead
of the WRITE but accidentally positioned after the WRITE, the READ would return the new
data, not the original data prior to being overwritten. These are significant data coherency
mistakes.
To avoid address collisions, READs or WRITEs that access the same chip select, bank and
row as a command already in the command queue will be inserted into the command queue
after the original command, even if the new command is of a higher priority.
This factor may be enabled/disabled through the addr_cmp_en parameter and should only
be disabled if the system can guarantee coherency of READs and WRITEs.
Source ID collision
Each port is assigned a specific source ID that identifies the source uniquely. This allows the
Memory Controller to map data from/to the correct source/destination.
Note:
A source ID does contain port identification information which means that the rules for
placement are dependent on the requesting port. There will not be source ID collisions
between ports.
In general, commands of the same type from the same source ID will be placed in the
command queue in order. Therefore, a READ/WRITE command with the same source ID of
a READ/WRITE command being already in the command queue will be processed
afterward.
