LS_Analog to digital convertor (ADC)
RM0082
644/844
Doc ID 018672 Rev 1
29.3 Operating
sequence
29.3.1 Normal
mode
As long as POWER DOWN bit in ADC_STATUS_REG register (
) is set to
logic’0’, the ADC is inactive (disabled) and output latches contain last conversion.
Setting the POWER DOWN bit, the ADC enters in its functional mode after 50 us, when a
conversion can be then initiated setting the ENABLE bit in ADC_STATUS_REG register
(
At first, the 10 bit Conversion Data field of the AVERAGE_REG register (
) is
reset to the value 10'b1000000000 and the acquisition from selected analog input channel
occurs. After that, the conversion phase takes place, and 13 clock cycles are required for
one complete conversion.
At the end of conversion, the CONVERSION READY bit in ADC_STATUS_REG is set, and
the Conversion Data reading can begin. When the reading finishes, two different scenarios
could occur:
●
POWER DOWN bit is set (1'b1): the ENABLE bit is kept to 1'b1 (conversion enabled),
and next conversion can takes place without waiting for the start up time (50 us).
●
POWER DOWN bit is cleared (1'b0): the ADC is switched-off and next conversion
requires again a start up time (after setting the ENABLE bit in the ADC_STATUS_REG
register).
29.3.2 Enhanced
mode
In this mode (ENM bit = 1) is possible to perform conversions on selected channels in a
continuous way. The start of conversions may be external (EXT_SCAN_RATE bit = 1) or
internal. In the first case you need of an external signal to start the conversions while in the
internal mode is necessary to configure the SCAN_RATE register to set the number of APB
Clock cycles between the start of two scan conversions.
To read conversion results you need to read CHx_DATA registers. CHx_DATA[17] is the
VALID_DATA bit. It's logic ‘1’ when read data is valid. It's logic ‘0’ in following cases:
●
ENM bit = 0;
●
CHANNEL_EN of relative channel = 0;
●
The controller is writing result in it.
On Channel 0 is possible to select a request to DMA (DMA_EN bit = 1) when conversion is
finished. In this case at the end of conversion on this channel, the controller will perform a
single request to DMA.When there will be next conversion on channel 0, the controller will
check for the end of last DMA transfer continuing with a new conversion on this channel only
if it is finished. In the other case the scan will continue with the other enabled channels.
