STMicroelectronics SPEAr300, Reference Manual

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LS_Fast IrDA controller RM0082
578/844 Doc ID 018672 Rev 1
26.5 Programming model
26.5.1 External pin connection
26.5.2 Register map
The FIrDA controller can be fully configured by programming its 32 bit wide registers which
can be accessed at the base address 0xD100_0000.
As depicted in Figure 59 , FIrDA controller registers can be logically arranged in three main
groups:
●
Control and status registers (listed in Table 496 ), for IrDA configuration,
● Data registers (listed in Table 497 ), containing the data bytes,
●
Interrupt and DMA registers (listed in Table 498 ), for managing interrupts and DMA
requests.
Table 495. External pin connection
Signal Ball
IrDA_RXD E3
IrDA_TXD F3
Table 496. FIrDA controller control and status registers summary
Name Offset Type Reset value Description
IrDA_CON 0x10 RW 32’h0 IrDA control.
IrDA_CONF 0x14 RW 32’h00020EA6 IrDA configuration.
IrDA_PARA 0x18 RW 32’h00460000 IrDA parameter.
IrDA_DV 0x1C RW 32’h0 IrDA divider.
IrDA_STAT 0x20 RO 32’h0 IrDA status.
IrDA_TFS 0x24 WO 32’h0 Transmission frame size.
IrDA_RFS 0x28 RO 32’h0 Reception frame size.
Table 497. FIrDA controller data registers summary
Name Offset Type Reset value Description
IrDA_TXB 0x2C WO 32’h0 Transmission buffer.
IrDA_RXB 0x30 RO 32’h0 Reception buffer.
Table 498. FIrDA controller interrupt and DMA registers summary
Name Offset Type Reset value Description
IrDA_IMSC 0xE8 RW 32’h0 Interrupt mask control.
IrDA_RIS 0xEC RO 32’h0 Raw interrupt status.
IrDA_MIS 0xF0 RO 32’h0 Masked interrupt status.