RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
125/844
If every port ordering parameters are set to the same value, the scan order will default to the
numbered port order.
10.5.6
Weighted round-robin arbitration summary
The Memory Controller weighted round-robin arbitration system merges the concepts of
round-robin operation, priority, relative priority and port ordering. The incoming commands
are separated into priority groups based on the priority of the associated port for that type of
command. Inside each priority group, the relative priority values are examined to settle the
arbitration winner. If relative priority values are the same and no individual command can be
selected, the scan order is used to select among the requests.
Finally the highest priority command incoming from the highest relative priority port, having
the highest location in the scan order, will be selected and sent to the Memory Controller
core.
For instance, let us consider the system described in
. The counters refer to the
ones inside each port priority group to guarantee that relative priorities are maintained. To
simplify, on assumes the command queue never be full and commands are only received at
priority level 0.
The behaviour is shown in
. The highest requesting port in the scan order always
wins arbitration and the scan order is dynamically modified whenever any port counter
reaches its allocated relative priority value.
Note:
If the command queue was considered, cycles where the command queue was full would
not have any arbitration winner and therefore the counter values and scan order would not
change on that cycle.
Table 61.
Port ordering example
Parameter
System B
System C
ahb0_port_ordering
3
3
ahb1_port_ordering
4
0
ahb2_port_ordering
5
5
ahb3_port_ordering
6
6
ahb4_port_ordering
7
7
ahb5_port_ordering
0
1
ahb6_port_ordering
2
0
ahb7_port_ordering
1
0
Port Scan Order
P5-P7-P6-P0-P1-P2-P3-P4
P1-P6-P7-P5-P0-P2-P3-P4
Table 62.
System D specifications
Parameter
Port 0
Port 1
Port 2
Port 3
ahbX_priority0_relative_priority
4
3
2
1
ahbX_port_ordering
0
1
2
3
