RS_Telecom IP
RM0082
778/844
Doc ID 018672 Rev 1
The first three signals can be divided by the I2S_CLK block to adjust to the correct
frequency. In slave mode, the clock will be received on I2S_CLK pin.
●
Two banks are used to exchange the samples with the processor. The number of
sample stored in a buffer is programmable (please refer to
). When the I2S interface reads and stores the data in one bank,
the processor is owner of the other bank, allowing it to read the received data before
writing a buffer to be played.
●
When the two banks are switched, this can generate an interrupt or DMA transfer.
When this event occurs, if the processer has not finished to process the previous input
buffer and store the new output buffer, the processing is out of real time. It is the
responsibility of the software to check that operations are done in real time.
Figure 98.
I2S data reception and transmission (8 bits)
In order to avoid synchronization problems, the MSB of the buffer address is managed by
the device itself to allow the processor to always access the correct buffer automatically. The
processor always accesses the right bank seen between 0000 and 0FFF.
To memory
From memory
LRCK
DIN
Received data
Shifted left data
Data to transmit
Shifted left data
DOUT
