STMicroelectronics SPEAr300, Reference Manual

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RM0082 AS_Cryptographic co-processor (C3)
Doc ID 018672 Rev 1 367/844
Bit 31 to 0 - Channel n status (CnS)
The status of each Channel is mirrored in these bits. The lower 16 bits (bits 15 to 0) are the
same ones as found in the Instruction Dispatcher Status and Control Register (ID_SCR)
and in the System Status and Control Register (SYS_SCR). See the Instruction Dispatcher
registers description (section 3) for more details. The upper 16 bits (bits 31 to 16) represents
the status of Channels 8 to 15. Using this register is the only way to know the status of
Channels 8 to 15.
Hardware Version and Revision Registers (SYS_VER)
The Hardware Version and Revision Register (SYS_VER) contain the RTL source version
from which the Hardware was generated.
Hi Bit CnSH LoBit CnSL Description
0 0 Not Present: This Channel does not exist in Hardware.
1 0 Idle: The Channel is idle and instructions can be dispatched to it.
1 1
Busy: The Channel is executing instructions dispatched by an
Instruction Dispatcher.
0 1
Error: The Channel is in error state, use Channel registers to know
the cause.
Bit 31 30 29 28 27 26 25 24
Symbol V7 V6 V5 V4 V3 V2 V1 V0
Initial Value 0 0 0 0 0 0 1 1
Type RO RO RO RO RO RO RO RO
Bit 23 22 21 20 19 18 17 16
Symbol R7 R6 R5 R4 R3 R2 R1 R0
Initial Value R7 R7 R7 R7 R7 R7 R7 R7
Type RO RO RO RO RO RO RO RO
Bit 15 14 13 12 11 10 9 8
Symbol S15 S14 S13 S12 S11 S10 S9 S8
Initial Value S15 S14 S13 S12 S11 S10 S9 S8
Type RO RO RO RO RO RO RO RO
Bit 7 6 5 4 3 2 1 0
Symbol S7 S6 S5 S4 S3 S2 S1 S0