RS_SDIO controller
RM0082
712/844
Doc ID 018672 Rev 1
Table 633.
CLKCTRL register bit assignments
Bit
Name
Reset
value
Type
Description
[15:08]
SDCLKFSEL
8’h00
RW
This register is used to select the frequency of the
SDCLK pin. The frequency is not programmed
directly; rather this register holds the divisor of the
Base Clock Frequency For SD clock in the
capabilities register. Only the following settings are
allowed.
8’h80 - base clock divided by 256
8’h40 - base clock divided by 128
8’h20 - base clock divided by 64
8’h10 - base clock divided by 32
8’h08 - base clock divided by 16
8’h04 - base clock divided by 8
8’h02 - base clock divided by 4
8’h01 - base clock divided by 2
8’h00 - base clock (48 MHz)
Setting 0x00 specifies the highest frequency of the
SD Clock. When setting multiple bits, the most
significant bit is used as the divisor. But multiple bits
should not be set. According to the Physical Layer
Specification, the maximum SD Clock frequency is
25 MHz in normal speed mode and 50MHz in high
speed mode, and shall never exceed this limit. The
frequency of the SDCLK is set by the following
formula:
Clock Frequency = (Baseclock) / divisor.
Thus choose the smallest possible divisor which
results in a clock frequency that is less than or
equal to the target frequency.
Maximum Frequency = 48 MHz (base clock)
Minimum Frequency = 187.5 kHz
(48 MHz / 256)
[07:03]
-
-
Rsvd
Reserved
[02]
SDCLKEN
1’h0
RW
The HC shall stop SDCLK when writing this bit to
logic ‘0’. SDCLK frequency Select can be changed
when this bit is logic ‘0’. Then, the HC shall
maintain the same clock frequency until SDCLK is
stopped (Stop at SDCLK = 1’b0). If the HC detects
the No Card state, this bit shall be cleared.
1’b1 - Enable
1’b0 - Disable
