RM0082
Clock & reset system
Doc ID 018672 Rev 1
203/844
The B parameter (random jitter) is the value of one sigma of this normal distribution, while A
parameter is the deterministic jitter.
Single period jitter can be defined as the difference of the Tmax and Tmin, where Tmax is
maximum time period of the CLOCK and Tmin is the minimum time period of the CLOCK.
Cycle-to-cycle jitter is the cycle time variation between adjacent cycles over a random
sample of adjacent clock cycle pairs.
11.2
Clock distribution scheme
11.2.1 Processor
clock
Figure 14.
Processor clock
According to the state machine (see
Chapter 14: BS_System controller
for full detail) the
CPU clock can be derived from the following sources:
●
External crystal (24 MHz)
●
PLL1 (up to 333 MHz)
●
RTC crystal (32.768 kHz)
By various setting inside the miscellaneous registers is possible to define the frequency of
the PLL1 and also the ratio between the CPU clock and the BUS (HCLK) clock.
11.2.2 DDR
controller
clock
Figure 15.
DDR Controller Clock
HCLK
External Crystal (24MHz)
PLL1 (up to 333MHz)
RTC Crystal (32.768KHz)
Source Clock Selector
(From Sys Controller)
Frequency Selector
(From Misc Registers)
CPU_CLK
DDR_CLK
CLK_PLL1
HCLK
CLK Selector
(From MISC Registers)
CLK_PLL2
Memory Controller
Clock
DLL Mem.
Ctrl
