RM0082
LS_Universal asynchronous receiver/transmitter (UART)
Doc ID 018672 Rev 1
589/844
27
LS_Universal asynchronous receiver/transmitter
(UART)
27.1 Overview
SPEAr300 has single UART:
●
UART has a maximum baud rate of 3 Mbps and minimum baud rate of 45 bps. It
supports modem control and hardware flow control signals.
Each UART is intended to perform:
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Serial-to-parallel conversion on data received from a peripheral device;
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Parallel-to-serial conversion on data transmitted to the peripheral device.
Main features of each UART are listed below:
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Separate 16 x 8 (16 location deep x 8 bit wide) transmit and 16 x 12 receive FIFOs to
reduce CPU interrupts;
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Provides programmable FIFO disabling for 1-byte depth;
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Programmable baud rate generator that enables division of the reference clock by (1 x
16) to (65535 x16) and generates an internal x16 clock. The divisor can be a fractional
number.
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Provides standard asynchronous communication bits (start, stop and parity) which are
added prior transmission and removed on reception;
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Supplies independent masking of transmit or receive FIFO, receive timeout, and error
condition interrupts. UART also supports modem status.
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Supports DMA;
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Detects false start bit;
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Generates and detects line break;
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UART supports the modem control functions CTS,DCD,DSR,RTS, DTS and RI.
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UART provides programmable hardware flow control.
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Provides fully-programmable serial interface with the subsequent characteristics:
–
data can be 5, 6, 7 or 8 bits;
–
even, odd, stick or no-parity bit generation and detection;
–
1 or 2 stop bit generation;
–
UART baud rate generation dc up to UARTCLK_max_freq/16 (
PRPH_CLK_CFG register bit assignments
(Bit 04) in Miscellaneous chapter).
–
UART1 - UART5 baud rate generation up to 5 Mbps
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Provides some programmable parameters, such as:
–
communication baud rate, integer and fractional parts;
–
number of data bits;
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parity mode;
–
FIFO enable (16 deep) or disable (1 deep);
–
FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4 and 7/8;
