STMicroelectronics SPEAr300, Reference Manual

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DDR memory controller (MPMC) RM0082
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priority relax counters could reach their specified value simultaneously. In this case, the
lower priority command will be arbitrated first and the higher priority command afterward.
This situation could modify the arbitration latency slightly, causing it to be longer than the
expected value in the priority relax parameter.
Consider the System F as described in Table 66 . The same conditions apply as for the
previous example. The command queue is considered to never be full, commands from
ports 0, 1, 2 and 3 are only received at priority level 0, and commands from ports 4 and 5
are only received at priority 1.
Table 67 shows the system behavior. The exact settings of the latency control and priority
relax parameters are not displayed. Relaxed Ports column indicates instead which ports, if
any, have hit their priority relax values. The following cycles are important to observe:
●
Cycles 1 and 7 : A port relaxes while a higher priority request and a higher scan order
request are both present. The relaxed port still wins arbitration.
● Cycle 4 : Two ports of the same priority relax. The higher scan order request wins
arbitration.
●
Cycle 5 : Two ports of different priorities relax. The lower priority port that relaxed wins
arbitration. The higher priority port that relaxed will maintain its relax condition, and win
arbitration in the next cycle.
Table 66. System F specifications
Parameter Port 0 Port 1 Port 2 Port 3 Port 4 Port 5
ahbX_priority0_relative_priority 4 3 2 1 1 1
ahbX_priority1_relative_priority 1 1 1 1 2 1
ahbX_port_ordering 0 1 2 3 5 4
Table 67. System F operation with priority relaxing
Cycle
Ports Requesting
Relaxed
Ports Arbitration
Winner
Next Counter
Next Scan Order
P
0 P
1 P
2 P
3 P
4 P
5 P
0 P
1 P
2 P
3 P
4 P
5
Priority 0: P0-P1-P2-
P3
Priority 1: P5-P4
0 Y Y Y P2 0 0 1 0 0 0
P0-P1-P2-P3
P5-P4
1 Y Y Y P5 P5 0 0 1 0 0 1
P0-P1-P2-P3
P5-P4
2 Y Y Y P2 0 0 2 0 0 0
P0-P1-P3-P2
P4-P5
3 Y Y Y P1 0 1 0 0 0 0
P0-P1-P3-P2
P4-P5
4 Y Y Y P4, P5 P4 0 1 0 0 1 0
P0-P1-P3-P2
P4-P5