RS_Telecom IP
RM0082
806/844
Doc ID 018672 Rev 1
When a source generates an interrupt request it is the processor that must clear it in the
interrupt handler.
The above interrupts are ORed to generate interrupt on RAS_INT_out(0) - IRQ28.
34.7
Action memory content description
The action memory contains for any timeslot the necessary parameters to use this timeslot,
both for input and for output.
The action memory is defined in the address range - 0x5001_0000 to 0x5001_0FFF.
Each word (corresponding to a specific time slot) of the memory is described as -
RESET: all ‘0’
[11:09]
Reserved
Interrupt requests from IPs after filtering through interrupt mask
register.
[08]
IT_GPIO
[07]
IT_KB
[06]
Reserved
[05]
Reserved
[04]
Reserved
[03]
ITtdm
[02]
ITi2s
[01]
ITch
[00]
Itp
Table 726.
Interrupt status register (Offset 0x58) (continued)
Bits
Name
Comments
Table 727.
Action memory
Bits
Name
Comments
[31:29]
Reserved
[28]
LSBin
informs if the DIN data must be latched first bit in MSB (shift
left) or first bit in LSB (shift right).
LSBin = 0
:
data is received MSB first (usual in voice)
LSBin = 1
:
data is received LSB first.
[27]
LSBout
informs if the DOUT data must be MSB in first bit (shift left) or
LSB in first bit (shift right).
LSBout = 0
:
data is sent MSB first (usual in voice)
LSBout = 1
:
data is sent LSB first.
