DDR memory controller (MPMC)
RM0082
140/844
Doc ID 018672 Rev 1
Refresh masking
Regular refresh commands will be issued at the same intervals as the Memory Controller is
operating normally, is idle, or is in any of the low power modes. However, for memory arrays
with multiple chip selects, the Memory Controller can mask refreshes during any of the low
power modes. By setting bits of the lowpower_refresh_enable parameter to 1'b1, auto-
refreshes will be masked for the associated chip selects.
User should ensure that refreshes are not constantly masked, and that each chip select is
refreshed periodically.
Low power and clock forwarding
The Memory Controller implements a clock forwarding scheme, which eliminates the need
for a de-skew PLL and reduces the overall power consumption of the device. Controllers that
are configured for low power should also be configured for clock forwarding.
Mobile DDR/SDRAM devices
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Enabling mobile usage
When the device is used inside a mobile device, the parameter en_lowpower_mode
must be set to 1'b1. This enables the Memory Controller to use the initialization
sequence and EMRS addressing suitable for mobile equipments. When the
en_lowpower_mode parameter is cleared to 1'b0, a standard DDR SDRAM or SDRAM
device may be used.
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Partial array self-refresh
For mobile applications, the Memory Controller is able to support refresh operations to
subsections of the memory array. To simplify this duty, separate parameters are
provided to supply the EMRS data for each chip select. These are the emrs_data_X
parameters, where X represents the chip select.
Having separate control parameters for the EMRS data allows the individual chips to
set their own masked refresh. The write_modereg parameter controls the writing of this
EMRS data into the registers. When write_modereg is set to 1'b1 initially, the EMRS
register of chip select 0 will be written. Each subsequent setting of the write_modereg
parameter to 1'b1 will write the EMRS register of the next chip select (1, 2, then 3).
Note:
The Memory Controller does not check if operations attempt to access addresses outside
the refresh ranges set by the EMRS registers, so any access to these addresses may result
in corrupt or lost data.
10.8 Additional
features
10.8.1
Out-of-range address checking
It is possible that the master attempts to write to an invalid address. For this reason, all
incoming addresses are always checked against the addressable physical memory space. If
a transaction is addressed to an out-of-range memory location, bit 0 of the int_status
parameter will be set to 1'b1 to alert the user of this condition. The Memory Controller will
record the address, source ID, length and type of transaction that caused the out-of-range
interrupt in the out_of_range_addr, out_of_range_source_id, out_of_range_length and
out_of_range_type parameters.
