Clock & reset system
RM0082
202/844
Doc ID 018672 Rev 1
11.1 Clock
generation
scheme
Figure 13.
Clock generation scheme
11.1.1
Jitter at PLL output clock
The three clocks outgoing from the PLLs have a jitter that can be calculated using the
formula contained in the figure below.
*The jitter specification holds true only up to 50mV noise (peak to peak) on power supply.
**Depending on the requirements of the application, please refer to the following table for
estimating the value of N.
The peak to peak jitter is a statistical effect. If a large number of samples (of the clock jitter)
are measured the values will usually hold to a normal distribution. The interpretation of peak
to peak jitter depends upon the effects of the jitter.
RTC
PLL1
PLL2
PLL3
24MHz
32.768KHz
OSC
CLK32MHz
DIV1/
DIV2/
DIV3
Min 333 MHz
Min 166 MHz
Min 83 MHz
333 MHz
CPU_CLK
HCLK
PCLK
DDR_CLK
CLK12MHz
CLK30MHz
CLK48MHz
DIV1/
DIV2/
DIV3
Table 154.
Jitter at PLL output clock
Jitter Type
Jitter
Due to
Supply
Noise
(Peak)
Jitter Due
to Device
Noise (I
Sigma)
Total Jitter (Peak
to Peak)
Total Jitter at PLL Output Clock @ 333
MHz Input @ 24 MHz N@3
A*
B
+/-(A + N * B)**
A*
B
+/-(A + 3 * B)**
Single
Period
Jitter
30 ps
0.06% of
output
time
period
+/-(A + N * B)
30 ps
1.8 ps
+/-35.4 ps
Cycle to
Cycle Jitter
30 ps
0.12% of
output
time
period
+/- (A + N * B)
30 ps
3.6 ps
+/- 40.8 ps
