RM0082
DDR memory controller (MPMC)
Doc ID 018672 Rev 1
187/844
auto_refresh_mode [0]
Sets the mode to be performed as the automatic refresh will occur. If
auto_refresh_mode is set and a refresh is required to memory, the
Memory Controller will either delay this refresh until the end of the
current transaction has been reached (if the transaction is fully
contained inside a single page), or until the current transaction hits the
end of the current page.
1'b0 - Issue refresh on the next DRAM burst boundary, even if the
current command is not complete.
1'b1 - Issue refresh on the next command boundary.
bank_split_en [0]
Enables bank splitting as a condition when using the placement logic to
fill the command queue.
1'b0 - Disabled
1'b1 - Enabled
big_endian_en [0]
Selects the byte ordering for Memory Controllers with programmable
endian setting.
1'b0 - Little Endian
1'b1 - Big Endian
caslat [2:0]
Sets the CAS latency encoding that the memory uses. The binary value
of this parameter is dependent on the memory device, since the same
caslat value may have different meanings to different memories. This
will be programmed into the DRAM devices at initialization. The CAS
encoding will be specified in the DRAM spec sheet, and should
correspond to the caslat_lin parameter.
caslat_lin [3:0]
Sets the CAS latency linear value as half-cycles expressed increments
number.
This sets an internal adjustment for the delay since the READ
command is sent from the Memory Controller until data will be received
back. The timing window inside which the data is captured is a fixed
length. The caslat_lin parameter adjusts the start of this data capture
window.
Not all linear values are supported by every memory devices: please
refer to the specification for the memory devices being actually used.
4'b0000 - 4'b0001 - Reserved
4'b0010 -1 cycle
4'b0011 - 1.5 cycles
4'b0100 - 2 cycles
4'b0101 - 2.5 cycles
4'b0110 - 3 cycles
4'b0111 - 3.5 cycles
4'b1000 - 4 cycles
4'b1001 - 4.5 cycles
4'b1010 - 5 cycles
4'b1011 - 5.5 cycles
4'b1100 - 6 cycles
4'b1101 - 6.5 cycles
4'b1110 - 7 cycles
4'b1111 - 7.5 cycles
Table 153.
Memory controller parameters (continued)
Parameter
Description
