BS_General purpose timers
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Doc ID 018672 Rev 1
17
BS_General purpose timers
17.1 Overview
SPEAr300 provides three general purpose timers (GPTs) acting as APB slaves (one local
timer in the CPU subsystem and two other timers in the basic subsystem).
Each GPT consists of 2 channels, each one made up of a programmable 16 bit counter and
a dedicated 8 bit timer clock prescaler. The programmable 8 bit prescaler performs a clock
division by 1 up to 256, and different input frequencies can be chosen through SPEAr300
configuration registers (so we can synthesize, for instance, a frequency range from 3.96 Hz
to 48 MHz).
Enabling a GPT (setting the ENABLE bit in TIMER_CONTROL register,
counter is firstly cleared and then it starts incrementing. When the counter reaches a pre-set
compare value (in TIMER_COMPARE register,
), two different modes of
operation are available (setting the MODE bit in TIMER_CONTROL register,
●
Auto-reload mode, an interrupt source is activated, the counter is automatically cleared
and then it restarts incrementing.
●
Single-shot mode, an interrupt source is activated, the counter is stopped and the GPT
is disabled.
●
Capture Mode, which is used for measurement of input timing signals. when a rising
transition occurs at the CPTRx(x=1,2), the actual counter value is stored into the rising
edge capture register and a dedicated interrupt source is activated. In the same way,
when a falling edge transition occurs at the CPTRx (=1,2) actual counter value is
stored into the falling edge capture register and an other interrupt source is also
activated. The processor can read the value stored in the two capture registers and
compute the duration of the rising to falling edge (or vice versa) time interval.
17.2 Programming
model
17.2.1 External
pin
connection
Table 253.
External pin connection
Subsystem
Basic address Signals
Ball
Usage
Note
CPU
0xF000_0000
-
-
-
Not available
