RM0082
BS_Serial memory interface
Doc ID 018672 Rev 1
305/844
t
SMI_CK
) for a byte, because of no mandatory extra commands (instruction opcode and
address).
Moreover, for AHB write burst transfers, the maximum latency for the 2
nd
transfer is (data
size + address bytes)
whereas, it is the same as data size for following transfers.
●
However, nominal latency can be increased by:
●
SMI transfer on going (read, write, read status register command or write enable
command),
●
Deselect time programming (field TCS in SMI_CR1 register), which adds (TCS + 1) ·
SMI_CK periods,
●
Busy / Idle transfer on AHB bus,
●
Fast Read (
) which adds 1 dummy byte,
●
Hold programming (field HOLD in SMI_CR1 register,
●
Boot delay time (
),
●
Frequency change,
●
Programming on-going.
15.7
How to boot from external memory
The device allows an external boot from a serial Flash only located at bank0 (which is
enabled after power-on reset). During the boot phase, the following instructions sequence is
automatically sent to bank0:
●
Release from deep power-down (opcode 8’hAB,
), in order to be able to boot
on this bank even if it was in deep power-down mode.
●
29 µs delay to ensure bank0 is successfully released.
●
Read status register (opcode 8’h05), in order to check that bank0 is neither in write nor
in erase cycle.
●
Read data bytes (opcode 8’h03) at memory start location (that is, 32’h0) with a 19 MHz
clock frequency.
Note:
1
All memory banks other than bank0 are disabled at reset and they must be enabled by
setting dedicated BE bits in SMI_CR1 register (
) before they can be
accessed.
2
If an AHB request occurs while either the WEN bit or the RSR bit (both in SMI_CR2 register,
) is set, the on-going command is first finished before the request from AHB is
sent to the memory.
