STMicroelectronics SPEAr300, Reference Manual

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LS_JPEG codec RM0082
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● EOC
End of Conversion (Active High)
● SCR
Synchronous Core Reset (Active High.
● LLI
Number of LLI (DMA parameter).for input data has to be programmed with.
● BNV
Number of bytes not valid in last word: if the total byte number is not an exact multiple
of 4, it will happen that 1, 2 or 3 bytes in the last 4-byte word will be meaningless.
● INT
Interrupt bit. Only a 0 can be written to this bit, having the effect of clearing the interrupt
bit. Trying to write a 1 to this bit will result in an unpredictable behavior.
25.4.9 JPGC bytes from Fifo to core register
This register contains the number of bytes that have been sent, at a given time, from the
FIFO In buffer to the codec core. The content of this register is cleared automatically when a
new coding process starts.
● NRX
Number of bytes sent from FIFO In to the Codec Core. This register is cleared when a
new encoding process starts.
Table 478. JPGC control status register bit assignments
Bit Name
Reset
value
Description
[31] EOC - End of Conversion (Active High)
[30] SCR -
Synchronous Core Reset (Active High). Write only field. Writing 1
on this bit will reset & disable both CODEC and controller. Clear this
bit to enable CODEC.
[29:18] Reserved -
[17:03] LLI -
Number of LLI (DMA parameter). This field is only writable and not
readable
[02:01] BNV - Number of bytes not valid in last word.
[00] INT -
Interrupt bit. It is possible to write only 0 in this bit to clear the
interrupt bit. It is wrong to write 1 in this field.
Table 479. JPGC bytes from Fifo to core register bit assignments
Bit Name
Reset
value
Description
[31:00] NRX - Number of bytes from FIFO in to Codec Core.