STMicroelectronics SPEAr300, Reference Manual

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BS_Serial memory interface RM0082
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15 BS_Serial memory interface
15.1 Overview
SPEAr300 provides a serial memory interface (SMI), acting as an AHB slave interface (32,
16 or 8 bit) to SPI-compatible off-chip memories. SMI allows the CPU to use these serial
memories for both data storage and code execution.
Main features of SMI are:
●
Supports a group of SPI-compatible Flash and EEPROM devices, namely:
– STMicroelectronics M25Pxxx, M45Pxxx,
– STMicroelectronics M95xxx, except M95040, M95020 and M95010,
– ATMEL AT25Fxx,
– YMC Y25Fxx,
– SST SST25LFxx.
●
Acts always as a SPI master and up to 2 SPI slave memory devices are supported
(through as many chip select signals), with up to 16 MB address space each.
● The SMI clock signal (SMICLK) is generated by SMI and input to all slaves.
●
SMICLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode), and it
can be controlled by a programmable 7 bits prescaler allowing then 127 different clock
frequencies.
15.2 Block diagram
Figure 25 shows the block diagram of SMI.
SMI consists of two main functions which are detailed in the following sections:
●
The Clock Prescaler ( Section 15.3.1 ).
● The Data Processing and Control ( Section 15.3.2 ).