RM0082
BS_Serial memory interface
Doc ID 018672 Rev 1
299/844
Figure 25.
SMI block diagram
15.3
Main functions description
15.3.1 Clock
prescaler
The SMI clock prescaler block allows to set-up the memory clock SMI_CK using the AHB
clock HCLK, as detailed in
.
15.3.2
Data processing and control
The SMI data processing and control block represents the logic controlling the transfer of
data between SPI-compatible off-chip memory and AHB bus. Transfer rules through both
AHB-to-SMI and SMI-to-memory interfaces. Different data transfer mode between SPI-
compatible off-chip memory and AHB bus are detailed in
.
AHB-to-SMI interface
Acting as an AHB slave interface, the SMI is accessed by AHB master through AHB bus.
The following rules apply to this interface:
●
Endianness is fixed to little-endian.
●
SPLIT / RETRY responses from AHB slave (that is., the SMI) are not supported.
●
Size of data transfers to external serial memories can be byte, half-word or word (that
is, 8, 16 or 32 bit).
●
Size of data transfers to SMI registers must be 32 bits.
●
Read requests: all types of BURST defined by AHB protocol are supported (single,
wrapping and incrementing). Please note that wrapping bursts take more time than
incrementing bursts, as there is a break in the address increment.
SMI Clock
Prescaler
(1 to 127)
Data,
command
Bank select
Transmit Register
Receive Register/
Status Regsiter
Control and
Status Register
AHB Slave
Interface
SMI Data processing
and Control
Clock
SPI-
Compatible
Memories
AM
BA
A
H
B B
us
Data,
Status
