RM0082
Product overview
Doc ID 018672 Rev 1
4.7 Basic
subsystem
●
Eight high performance DMA channels with two AHB interfaces to parallelize the
activity when two channels are working at the same time.
●
32 Kbyte of ROM.
●
Serial Flash interface capable of working up to 50 Mbps.
●
Four timers with programmable prescaler.
●
Watchdog timer.
●
RTC with separate power supply allowing battery connection
●
Upto 6 GPIOs bidirectional signals with interrupt capability
●
System controller and miscellaneous registers array allowing a full configurability of the
system.
4.8
High speed connectivity subsystem
●
Ethernet MAC controller that can support 10/100 Mbps with external PHY.
●
One USB host controller compatible with USB 2.0 high-speed specification managing
two ports. The peripheral has dedicated channel to the multi-port memory controller
and two slave ports for CPU programming (OHCI and EHCI). The PHYs are
embedded. One host controller at a time can perform high speed transfer.
●
One USB device compatible with USB 2.0 high-speed specifications.
A dedicated channel connects the peripheral with the multi-port memory controller and
registers and internal FIFO are accessible from the CPU through the main AHB bus.
An USB-Plug detector block is also available to detect the presence of the VBUS
voltage.
The port is provided with sixteen physical endpoints and proper configurations to
achieve logical endpoints.
4.9
Low speed connectivity subsystem
●
One UART with a data rate up to 3 Mbps.
●
IrDA controller with a data rate from 9.6 Kbps to 4 Mbps.
●
One Synchronous Serial Peripheral (SSP) controller capable of operating in master
and slave (Motorola-Texas-National) with a data rate up to 40 Mbps.
●
One I
2
C controller capable of operating in master and slave mode and covering all the
possible speeds (data rates) (high, fast and low).
●
JPEG CODEC accelerator (1clk per pixel).
●
57 Kbyte of static RAM.
●
ADC converter (1 µs/1 MSPS) with 8 analog input channels, 10 bit approximation.
