HS_USB 2.0 device
RM0082
484/844
Doc ID 018672 Rev 1
23.6
Operation modes In DMA mode
23.6.1 Packet-per-buffer
mode
In
packet-per-buffer
mode (alternate to buffer fill mode,
Buffer fill mode (OUT) on page 484
the DMA transfers packet by packet to various addresses as indicated by the descriptor,
implementing then a true scatter-gather mechanism.
A descriptor update can happen either at the end of each packet transfer or at the end of the
descriptor chain only. As a results, the application may be interrupted either after processing
each descriptor or at the end of a descriptor chain, respectively. In particular, setting to 1‘b1
the DU bit of the global CSRs’
Device control register on page 492
, it enables descriptor
updating and application interrupt to the software at the end of each packet.
23.6.2 Buffer
fill mode (OUT)
Enabling the
buffer fill
mode (setting the bit BF in the global CSRs’
, the DMA transfers all packets to the large buffer whose address is indicated by
the single out data memory structure descriptor. This DMA mode of operation requires fewer
memory accesses than packet-per-buffer with descriptor update mode
above, increasing the throughput.
The DMA controller updates buffer status when a short packet is received, and
simultaneously sends an interrupt to the application.
23.6.3
Buffer fill mode (IN)
In case of in transactions, the DMA buffer fill mode can be entered by using the packet-per-
buffer mode with only one descriptor indicating:
●
The system memory starting address,
●
The number of bytes to be transferred to the USB host (the tx bytes can be greater than
one packet),
●
The L bit set in the status quadlet.
The DMA controller updates buffer status after all data has been transferred to the TxFIFO.
The UDC-AHB subsystem then sends an interrupt to the application.
23.6.4 Threshold
enable
The
threshold enable
feature is used for transferring packets in the out direction for DMA
operation only. There is no threshold enable for the in direction.
Note:
In this context, thresholding means emptying the out RxFIFO as soon as it receives a
certain number (the threshold value) of 32 bit words.
Thresholding is enabled by setting to 1‘b1 the THE bit in the global CSRs’
. Moreover, the threshold value is programmed by setting the THLEN 8
bit in the same device control register. As mentioned, the threshold value is the number of
32 bit words (quadlets) that must be received by the RxFIFO before the DMA can start the
transfer.
When thresholding is disabled (bit THE set to 1‘b0), then the DMA waits for the complete
packet before starting the data transfer. In contrast, if thresholding is enabled, the transfer of
the packet to host memory starts before the validity of the packet is assessed. If the packet
