DDR memory controller (MPMC)
RM0082
186/844
Doc ID 018672 Rev 1
ahbX_rdcnt [10:0]
Holds the number of bytes to be responded to AHB port X after an
INCR READ AHB command. The AHB logic will subdivide an INCR
request into Memory Controller core commands of the size of this
parameter. The logic will continue requesting bursts of this size as soon
as the previous request has been received by the AHB port. If the INCR
command is terminated on an unnatural boundary, the logic will discard
the unnecessary words.
The value defined in this parameter should be a multiple of the number
of bytes in the AHB port width. Clearing this parameter will cause the
port to issue commands of 0 length to the Memory Controller core,
which the core interprets as the pre-configured value of 1024 bytes.
ahbX_w_priority [2:0]
Sets the priority of WRITE commands from AHB port X. A value of 0 is
the highest priority.
ahbX_wrcnt [10:0]
Holds the number of bytes to send to the Memory Controller core from
AHB port X for an INCR WRITE AHB command. The AHB logic will
subdivide an INCR request into Memory Controller core commands of
the size of this parameter. The logic will continue sending bursts of this
size as the previous request has been transmitted by the AHB port. If
the INCR command is terminated on an unnatural boundary, the logic
will discard the unnecessary words.
The value defined in this parameter should be a multiple of the number
of bytes in the AHB port width. Clearing this parameter will cause the
port to issue commands of 0 length to the Memory Controller core,
which the core interprets as the pre-configured value of 1024 bytes.
ap [0]
Enables auto pre-charge mode for DRAM devices.
(1)
'b0 - Auto pre-charge mode disabled. Memory banks will stay open until
another request requires this bank, the maximum open time (tras_max)
has elapsed, or a refresh command closes all the banks.
'b1 - Auto pre-charge mode enabled. All READ and WRITE
transactions must be terminated by an auto pre-charge command.
If a transaction consists of multiple READ or write bursts, only the last
command is issued with an auto pre-charge.
aprebit [3:0]
Defines the location of the auto pre-charge bit in the DRAM address in
decimal encoding.
arefresh [0]
Begins an automatic refresh to the DRAM devices based on the setting
of the auto_refresh_mode parameter. If there are any open banks when
this parameter is set, the Memory Controller will automatically close
these banks before issuing the auto-refresh command. This parameter
will always read back 'b0.
1'b0 - No action
1'b1 - Issue refresh to the DRAM devices
Table 153.
Memory controller parameters (continued)
Parameter
Description
