RS_Color liquid crystal display controller (CLCD)
RM0082
746/844
Doc ID 018672 Rev 1
33.5.8 Panel
clock
generator
The output of the panel clock generator block is the panel clock. This is a divided down
version of CLCDCLK. It can be programmed in the range CLCDCLK/2 to CLCDCLK/33 to
match the bpp data rate of the LCD panel.
33.5.9 Timing
controller
The primary function of the timing controller block is to generate the horizontal and vertical
timing panel signals. It also provides panel bias/enable signal. These timings are all register
programmable through the AMBA AHB slave interface.
33.5.10 Interrupt
generation
The CLCD provides four individually maskable interrupts and a single combined interrupt.
The single combined interrupt is asserted if any of the combined interrupts are asserted and
unmasked. The Interrupts are generated for the following events:
●
Master bus error
●
Vertical compare
●
LCD next base address update
●
FIFO underflow
Master bus error interrupt
The master bus error interrupt is asserted when an ERROR response is received by the
master interface during a transaction with a slave. When such an error is encountered, the
master interface enters an error state and remains in this state until clearance of the error
has been signaled to it.
Vertical compare interrupt
The vertical compare interrupt asserts when one of four vertical display regions, selected
using the LCD Control Register (
), is reached.
●
vertical synchronization
●
back porch
●
active video
●
front porch.
LCD Next base address update interrupt
The LCD next base address update interrupt asserts when either the LCDUPBASE or
LCDLPBASE values have been transferred to the LCDUPCURR or LCDLPCURR
incrementers respectively. This signals to the system that it is safe to update the
LCDUPBASE or the LCDLPBASE Registers with new frame base addresses if required.
FIFO underflow interrupt
The FIFO underflow interrupt asserts when internal data is requested from an empty DMA
FIFO. Internally, individual upper and lower panel DMA FIFO underflow interrupt signals are
generated and CLCDFUFINTR is the single combined version of these.
