STMicroelectronics SPEAr300, Reference Manual

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RM0082 DDR memory controller (MPMC)
Doc ID 018672 Rev 1 143/844
10.9.2 Maximum address space
The maximum user address range is determined by the width of the memory datapath, the
number of chip select pins, and the address space of the DRAM device. The maximum
amount of memory can be calculated by the following formula:
Max Memory Bytes = ChipSelects x 2Address x NumBanks x DPWidthBytes
For this Memory Controller, the maximum values for these fields are as follows:
●
Chip Selects = 2
● Device Address = 15+14 (Row+Column)
●
Number of Banks = 8
● Datapath Width in Bytes = 2 bytes
As a result, the maximum accessible memory area is 16 GB.
10.9.3 Memory mapping to address space
The maximum allowable address space and mapping into the DRAM devices for the
Memory Controller is shown in
Figure 11 . This map corresponds to a memory device with
15 row bits and 14 column bits.
Figure 11. Memory map: Maximum
The addr_pins and column_size parameters can range from the maximum configured for
the Memory Controller to seven bits smaller than the maximum configured. This allows the
Memory Controller to work with a wide variety of memory device sizes.
The settings for the addr_pins and column_size parameters control how the address map is
used to decode the user address to the DRAM chip selects and row and column addresses.
The eight_bank_mode parameters control the address in DDR2 mode. It is assumed that
the values in these parameters never exceed the maximum values configured.
Using the example shown in Figure 11 , if the Memory Controller is wired to devices with 12
row pins and 12 column bits, the maximum accessible memory space would be reduced.
The accessible memory space for this configuration is 512 MB.
The address map for this configuration is shown in Figure 12 .
Note: Address bits 29 through 33 are not used. These bits are ignored when generating the
address to the DRAM devices
Figure 12. Alternate memory map
Note: The Chip Select, Row, Bank, and Column fields are used to address an entire memory
word, and the Datapath bits are used to address individual bytes within that user word. For
example, for a read starting at byte address 0x2, the Datapath bits must be defined as
3'b010 in order to address this byte directly. READs and WRITEs are memory word-aligned
if all the Datapath bits are 0.
Chip Select Row Bank Column Data Path
33
33 32 18 17 15 14 1 0 0
Chip Select Row Bank Column Data Path
33
29 28 28 27 16 15 12 1 0
Don’t care
13 0