STMicroelectronics SPEAr300, Reference Manual

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HS_Media independent interface (MII) RM0082
530/844 Doc ID 018672 Rev 1
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SF
Setting this bit, the transmission starts when a full frame resides in the Transmit FIFO. If
set, the TTC field in this register is ignored.
Note: This bit should be changed only when transmission is stopped.
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FTF
Setting this bit, the Transmit FIFO controller logic is reset and all data in the FIFO is
flushed (lost). When the flushing is fully completed, this bit is automatically cleared.
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TTC
This 3 bit field allows start of transmission when the frame size in the Transmit FIFO is
larger than the stated threshold, according to encoding below:
Table 436. Operation mode register bit assignments
Bit Name Reset Value Type Description
[31:22] Reserved - RO Read: undefined
[21] SF 1’h0 RW Store and Forward.
[20] FTF 1’h0 RW Flush Transmit FIFO.
[19:17] Reserved - RW Read: undefined.
[16:14] TTC 3’h0 RW Transmit Threshold Control.
[13] ST 1’h0 RW Start/Stop Transmission Command.
[12:11] RFD 2’h0 RW Threshold for De-activating Flow Control.
[10:09] RFA 2’h0 RW Threshold for Activating Flow Control.
[08] EFC 1’h0 RW Enable HW Flow Control.
[07] FEF 1’h0 RW Forward Error Frames.
[06] FUF 1’h0 RW Forward Undersized Good Frames.
[05] Reserved - RO Read: undefined.
[04:03] RTC 2’h0 RW Receive Threshold Control.
[02] OSF 1’h0 RW Operate on Second Frame.
[01] SR 1’h0 RW Start/Stop Receive.
[00] Reserved - RO Read: undefined.
Table 437. TTC field bit assignments
Value Threshold (Byte)
3‘b000 64
3‘b001 128
3‘b010 192
3‘b011 256
3‘b100 40
3‘b101 32