Renesas SH7616, Hardware Manual

Page: 843 / 935

Section 22 Electrical Characteristics
Rev. 2.00 Mar 09, 2006 page 817 of 906
REJ09B0292-0200
22.3.1 Clock Timing
Table 22.5 Clock Timing
Conditions: V
CC
= PLLV
CC
= 3.3 V ±0.3 V, PV
CC
= 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV
CC
≥≥≥≥
V
CC
,
V
SS
= PV
SS
= PLLV
SS
= 0 V, Ta = –20 to +75°C
Item Symbol Min Max Unit Figure
EXTAL clock input frequency f
EX
1 31.25 MHz 22.1
EXTAL clock input cycle time t
EXcyc
32 1000 ns
EXTAL clock input low-level pulse width t
EXL
8
* 1
, 12
* 2
— ns
EXTAL clock input high-level pulse width t
EXH
8
* 1
, 12
* 2
— ns
EXTAL clock input rise time t
EXR
— 4 ns
EXTAL clock input fall time t
EXF
— 4 ns
CKIO clock input frequency f
CKI
1 31.25 MHz 22.2
CKIO clock input cycle time t
CKIcyc
32 1000 ns
CKIO clock input low-level pulse width t
CKIL
8
* 3
, 12
* 4
— ns
CKIO clock input high-level pulse width t
CKIH
8
* 3
, 12
* 4
— ns
CKIO clock input rise time t
CKIR
— 4 ns
CKIO clock input fall time t
CKIF
— 4 ns
CKIO clock output frequency f
OP
1
* 5
, 8
* 6
62.5 MHz 22.3
CKIO clock output cycle time t
cyc
16 1000
* 5
,
125
* 6
ns
CKIO clock output low-level pulse width t
CKOL
3 — ns
CKIO clock output high-level pulse width t
CKOH
3 — ns
CKIO clock rise time t
CKOR
— 5 ns
CKIO clock fall time t
CKOF
— 5 ns
Power-on oscillation stabilization time t
OSC1
10 — ms 22.4
Standby recovery oscillation stabilization
time 1 t
OSC2
10 — ms 22.5
Standby recovery oscillation stabilization
time 2 t
OSC3
10 — ms 22.6
PLL synchronization stabilization time t
PLL
1 — ms 22.7
Notes: 1. When PLL circuit 2 is operating
2. When PLL circuit 2 is not used
3. When PLL circuit 1 is operating
4. When PLL circuit 1 is not used
5. When PLL circuit 1 and 2 are not used
6. When PLL circuit 1 or 2 is operating