Renesas SH7616, Hardware Manual

Page: 245 / 935

Section 6 User Break Controller (UBC)
Rev. 2.00 Mar 09, 2006 page 219 of 906
REJ09B0292-0200
6.2.13 Break Address Register D (BARD)
BARDH
Bit 15 14 13 12 11 10 9 8
BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1 0
BAD23 BAD22 BAD21 BAD20 BAD19 BAD18 BAD17 BAD16
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
BARDL
Bit 15 14 13 12 11 10 9 8
BAD15 BAD14 BAD13 BAD12 BAD11 BAD10 BAD9 BAD8
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 6 5 4 3 2 1 0
BAD7 BAD6 BAD5 BAD4 BAD3 BAD2 BAD1 BAD0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Break address register D (BARD) consists of two 16-bit readable/writable registers: break address
register DH (BARDH) and break address register DL (BARDL). BARDH specifies the upper half
(bits 31 to 16) of the address used as a channel D break condition, and BARDL specifies the lower
half (bits 15 to 0). The address bus connected to the X/Y memory can also be specified as a break
condition by making a setting in the XYED bit/XYSD bit in break bus cycle register D (BBRD).
When XYED = 0, BAD31 to BAD0 specify the address. When XYED = 1, the upper 16 bits
(BAD31 to BAD16) of BARD specify the X address bus, and the lower 16 bits (BAD15 to BAD0)
specify the Y address bus. BARDH and BARDL are initialized to H'0000 by a power-on reset;
after a manual reset, their values are undefined.