Section 18 User Debug Interface (H-UDI)
Rev. 2.00 Mar 09, 2006 page 778 of 906
REJ09B0292-0200
TDI
SDIR
SDSR
SDIR
SDSR
SDIR
SDSR
TDO
Shift register
Bit 31
Bit 15
Bit 16
Bit 0
Bit 15
Bit 15
Bit 0
Bit 0
• SDIR and SDSR serial data input/output
In Capture-IR, SDIR and SDSR are captured into the shift register, and in Shift-IR bits 0 to 15 of SDSR and
bits 0 to 15 of SDIR are output in that order from TDO.
In Update-IR, data input from TDI is written to SDIR, but not to SDSR.
.
.
.
.
.
.
Capture-IR
TDI
TDI
input
data
TDO
Shift register
Bit 31
Bit 15
Bit 16
Bit 0
Bit 15
Bit 0
.
.
.
Update-IR
Figure 18.6 Serial Data Input/Output (1)
Summary of Contents for SH7616
Page 10: ...Rev 2 00 Mar 09 2006 page x of xxvi ...
Page 132: ...Section 2 CPU Rev 2 00 Mar 09 2006 page 106 of 906 REJ09B0292 0200 ...
Page 568: ...Section 12 16 Bit Free Running Timer FRT Rev 2 00 Mar 09 2006 page 542 of 906 REJ09B0292 0200 ...
Page 582: ...Section 13 Watchdog Timer WDT Rev 2 00 Mar 09 2006 page 556 of 906 REJ09B0292 0200 ...
Page 706: ...Section 16 Serial I O SIO Rev 2 00 Mar 09 2006 page 680 of 906 REJ09B0292 0200 ...
Page 820: ...Section 19 Pin Function Controller PFC Rev 2 00 Mar 09 2006 page 794 of 906 REJ09B0292 0200 ...
Page 932: ...Appendix D Package Dimensions Rev 2 00 Mar 09 2006 page 906 of 906 REJ09B0292 0200 ...
Page 935: ...SH7616 Hardware Manual ...