Section 5 Interrupt Controller (INTC)
Rev. 2.00 Mar 09, 2006 page 162 of 906
REJ09B0292-0200
5.3.4
Interrupt Priority Level Setting Register D (IPRD)
Interrupt priority level setting register D (IPRD) is a 16-bit read/write register that sets the priority
levels (0–15) of on-chip peripheral module interrupts. IPRD is initialized to H'0000 by a reset. It is
not initialized in standby mode.
Bit:
15
14
13
12
11
10
9
8
TPU0IP3 TPU0IP2 TPU0IP1 TPU0IP0 TPU1IP3 TPU1IP2 TPU1IP1 TPU1IP0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
TPU2IP3 TPU2IP2 TPU2IP1 TPU2IP0 SCF1IP3 SCF1IP2 SCF1IP1 SCF1IP0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 4—16-Bit Timer Pulse Unit 0 to 2 (TPU0–TPU2) Interrupt Priority Level 3 to 0
(TPUnIP3–TPUnIP0, n = 0–2): These bits set the 16-bit timer pulse unit 0 to 2 (TPU0–TPU2)
interrupt priority levels. There are four bits for each interrupt, so the value can be set between 0
and 15.
Bits 3 to 0—Serial Communication Interface with FIFO 1 (SCIF1) Interrupt Priority Level 3 to 0
(SCF1IP3–SCF1IP0): These bits set the serial communication interface with FIFO 1 (SCIF1)
interrupt priority level. There are four bits, so the value can be set between 0 and 15.
Summary of Contents for SH7616
Page 10: ...Rev 2 00 Mar 09 2006 page x of xxvi ...
Page 132: ...Section 2 CPU Rev 2 00 Mar 09 2006 page 106 of 906 REJ09B0292 0200 ...
Page 568: ...Section 12 16 Bit Free Running Timer FRT Rev 2 00 Mar 09 2006 page 542 of 906 REJ09B0292 0200 ...
Page 582: ...Section 13 Watchdog Timer WDT Rev 2 00 Mar 09 2006 page 556 of 906 REJ09B0292 0200 ...
Page 706: ...Section 16 Serial I O SIO Rev 2 00 Mar 09 2006 page 680 of 906 REJ09B0292 0200 ...
Page 820: ...Section 19 Pin Function Controller PFC Rev 2 00 Mar 09 2006 page 794 of 906 REJ09B0292 0200 ...
Page 932: ...Appendix D Package Dimensions Rev 2 00 Mar 09 2006 page 906 of 906 REJ09B0292 0200 ...
Page 935: ...SH7616 Hardware Manual ...