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Section 7 Bus State Controller (BSC)

Rev. 2.00 Mar 09, 2006 page 256 of 906
REJ09B0292-0200

Address

Space

Memory

Size

H'24000000–H'25FFFFFF

CS2 space, cache-through
area

Ordinary space or
synchronous DRAM

32 Mbytes

H'26000000–H'27FFFFFF

CS3 space, cache-through
area

Ordinary space,
synchronous DRAM

, or

DRAM

32 Mbytes

H'28000000–H'29FFFFFF

CS4 space, cache-through
area

Ordinary space (I/O
device)

32 Mbytes

H'2A000000–H'3FFFFFFF Reserved

H'40000000–H'49FFFFFF

Associative purge space

160 Mbytes

H'4A000000–H'5FFFFFFF Reserved

H'60000000–H'7FFFFFFF Address array, read/write

space

512 Mbytes

H'80000000–H'BFFFFFFF Reserved

H'C0000000–H'C0000FFF Data array, read/write space

4 kbytes

H'C0001000–H'DFFFFFFF Reserved

H'E0000000–H'FFFEFFFF Reserved

H'FFFF0000–H'FFFF0FFF For setting synchronous

DRAM mode

4 kbytes

H'FFFF1000–H'FFFF7FFF Reserved

H'FFFF8000–H'FFFF8FFF For setting synchronous

DRAM mode

4 kbytes

H'FFFFC000–H'FFFFBFFF Reserved

H'FFFFFC00–H'FFFFFFFF On-chip peripheral modules

Notes: 1. Do not access reserved spaces, as operation cannot be guaranteed.

2. Bank-active mode is not supported for CS2 space synchronous DRAM access; auto-

precharge mode is always used.
Bank-active mode is supported for CS3 space synchronous DRAM access.

Summary of Contents for SH7616

Page 1: ... SuperH RISC engine Family SH7600 Series SH7616 HD6417616 Rev 2 00 REJ09B0292 0200 The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ...s a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein 5 Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is po...

Page 3: ... this manual require a basic knowledge of electrical circuits logic circuits and microcomputers Purpose The purpose of this manual is to give users an understanding of the hardware functions and electrical characteristics of the SH7616 Details of execution instructions can be found in the SH 1 SH 2 SH DSP Programming Manual which should be read in conjunction with the present manual Using this Man...

Page 4: ...ftware Manual REJ09B0171 0500O Users manuals for development tools Manual Title ADE No C C Complier Assembler Optimized Linkage Editor User s Manual REJ10B0152 0101 Simulator Debugger Users Manual REJ10B0210 0200 High performance Embedded Workshop Users Manual REJ10J0886 0300 Application Note Manual Title ADE No C C Complier REJ05B0463 0300 ...

Page 5: ...E000 H 1000EFFF On chip X RAM area 4 kbytes H 1001E000 H 1001EFFF On chip Y RAM area 4 kbytes 7 2 7 Individual Memory Control Register MCR Bits 1 and 15 For synchronous DRAM interface Bits 7 5 and 4 269 to 274 Description replaced 7 5 11 64 Mbit Synchronous DRAM 2 Mword 32 bit Connection 323 Description amended Synchronous DRAM Mode Settings To make mode settings for the synchronous DRAM write to ...

Page 6: ... occurrence of corresponding source to be indicated in the RFS7 bit in the receive descriptor Bits 6 to 0 Reserved These bits are always read as 0 The write value should always be 0 10 3 1 Descriptor List and Data Buffers Transmit Descriptor 0 TD0 450 Description amended TFS9 en Bit 27 Transmit Frame Error TFE Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 i...

Page 7: ... 10 3 1 Descriptor List and Data Buffers Receive Descriptor Figure 10 3 Relationship between Receive Descriptor and Receive Buffer 451 Figure amended Receive descriptor RACT RDLE RFP1 RFP0 RFE RFS 26 to RFS0 RD0 RBL RDL 0 0 31 31 30 29 28 26 27 31 RD1 RBA Padding 4 bytes RD2 16 15 ...

Page 8: ...FS0 These bits indicate the error status during frame reception RFS26 to RFS10 Reserved RFS9 Receive FIFO Overflow corresponds to RFOF bit in EESR RFS8 Reserve Abort Detect Note This bit is set to 1 when any of Receive Frame Status bit 9 bit 7 bits 4 to 0 is set When this bit is set the Receive Frame Error bit bit 27 RFE is set to 1 RFS7 Receive Multicast Address Frame corresponds to RMAF bit in E...

Page 9: ...nterrupt RDFI0 request and transmit data empty interrupt transmit control data register empty interrupt TDEI0 request Table 15 3 shows the interrupt sources and their relative priorities The RDFI0 and TDEI0 interrupts are enabled by the RIE RCIE TIE and TCIE bits respectively in SICTR The RERI0 and TERI0 interrupts cannot be disabled Table amended Interrupt Source Description DMAC Activation Prior...

Page 10: ...Rev 2 00 Mar 09 2006 page x of xxvi ...

Page 11: ...tial Values of Registers 40 2 2 Data Formats 41 2 2 1 Data Format in Registers 41 2 2 2 Data Formats in Memory 41 2 2 3 Immediate Data Format 42 2 2 4 DSP Type Data Formats 42 2 2 5 DSP Type Instructions and Data Formats 44 2 3 CPU Core Instruction Features 48 2 4 Instruction Formats 52 2 4 1 CPU Instruction Addressing Modes 52 2 4 2 DSP Data Addressing 56 2 4 3 Instruction Formats for CPU Instruc...

Page 12: ...Exception Handling 125 4 1 Overview 125 4 1 1 Types of Exception Handling and Priority Order 125 4 1 2 Exception Handling Operations 127 4 1 3 Exception Vector Table 128 4 2 Resets 131 4 2 1 Types of Resets 131 4 2 2 Power On Reset 131 4 2 3 Manual Reset 132 4 3 Address Errors 132 4 3 1 Sources of Address Errors 132 4 3 2 Address Error Exception Handling 134 4 4 Interrupts 135 4 4 1 Interrupt Sour...

Page 13: ...Vectors and Priority Order 152 5 3 Register Descriptions 159 5 3 1 Interrupt Priority Level Setting Register A IPRA 159 5 3 2 Interrupt Priority Level Setting Register B IPRB 160 5 3 3 Interrupt Priority Level Setting Register C IPRC 161 5 3 4 Interrupt Priority Level Setting Register D IPRD 162 5 3 5 Interrupt Priority Level Setting Register E IPRE 163 5 3 6 Vector Number Setting Register WDT VCR...

Page 14: ...eption Handling 192 5 5 Interrupt Response Time 192 5 6 Sampling of Pins IRL3 IRL0 194 5 7 Usage Notes 195 Section 6 User Break Controller UBC 199 6 1 Overview 199 6 1 1 Features 199 6 1 2 Block Diagram 200 6 1 3 Register Configuration 201 6 2 Register Descriptions 203 6 2 1 Break Address Register A BARA 203 6 2 2 Break Address Mask Register A BAMRA 204 6 2 3 Break Bus Cycle Register A BBRA 205 6 ...

Page 15: ...of Use 243 6 3 9 Usage Notes 247 Section 7 Bus State Controller BSC 249 7 1 Overview 249 7 1 1 Features 249 7 1 2 Block Diagram 251 7 1 3 Pin Configuration 252 7 1 4 Register Configuration 254 7 1 5 Address Map 255 7 2 Register Descriptions 257 7 2 1 Bus Control Register 1 BCR1 257 7 2 2 Bus Control Register 2 BCR2 260 7 2 3 Bus Control Register 3 BCR3 261 7 2 4 Wait Control Register 1 WCR1 263 7 ...

Page 16: ...erface 324 7 6 1 DRAM Direct Connection 324 7 6 2 Address Multiplexing 325 7 6 3 Basic Timing 326 7 6 4 Wait State Control 327 7 6 5 Burst Access 329 7 6 6 EDO Mode 332 7 6 7 DRAM Single Transfer 336 7 6 8 Refreshing 337 7 6 9 Power On Sequence 339 7 7 Burst ROM Interface 339 7 8 Idles between Cycles 343 7 9 Bus Arbitration 345 7 9 1 Master Mode 349 7 10 Additional Items 350 7 10 1 Resets 350 7 10...

Page 17: ... Access 370 8 5 Cache Use 371 8 5 1 Initialization 371 8 5 2 Purge of Specific Lines 372 8 5 3 Cache Data Coherency 372 8 5 4 Two Way Cache Mode 373 8 6 Usage Notes 374 8 6 1 Standby 374 8 6 2 Cache Control Register 374 Section 9 Ethernet Controller EtherC 375 9 1 Overview 375 9 1 1 Features 375 9 1 2 Configuration 376 9 1 3 Pin Configuration 378 9 1 4 Ethernet Controller Register Configuration 37...

Page 18: ... 9 3 2 Reception 404 9 3 3 MII Frame Timing 406 9 3 4 Accessing MII Registers 408 9 3 5 Magic Packet Detection 411 9 3 6 CPU Operating Mode and Ethernet Controller Operation 412 9 3 7 CAM Match Signal Input Function 413 9 4 Connection to PHY LSI 415 Section 10 Ethernet Controller Direct Memory Access Controller E DMAC 417 10 1 Overview 417 10 1 1 Features 417 10 1 2 Configuration 418 10 1 3 Descri...

Page 19: ...es 461 11 1 2 Block Diagram 463 11 1 3 Pin Configuration 464 11 1 4 Register Configuration 465 11 2 Register Descriptions 466 11 2 1 DMA Source Address Registers 0 and 1 SAR0 SAR1 466 11 2 2 DMA Destination Address Registers 0 and 1 DAR0 DAR1 466 11 2 3 DMA Transfer Count Registers 0 and 1 TCR0 TCR1 467 11 2 4 DMA Channel Control Registers 0 and 1 CHCR0 CHCR1 467 11 2 5 DMA Vector Number Registers...

Page 20: ...tput Compare Control Register TOCR 527 12 3 CPU Interface 528 12 4 Operation 531 12 4 1 FRC Count Timing 531 12 4 2 Output Timing for Output Compare 532 12 4 3 FRC Clear Timing 532 12 4 4 Input Capture Input Timing 533 12 4 5 Input Capture Flag ICF Setting Timing 534 12 4 6 Output Compare Flag OCFA OCFB Setting Timing 534 12 4 7 Timer Overflow Flag OVF Setting Timing 535 12 5 Interrupt Sources 536...

Page 21: ...atchdog Timer Mode and Interval Timer Mode 554 13 4 4 System Reset with WDTOVF 555 13 4 5 Internal Reset in Watchdog Timer Mode 555 Section 14 Serial Communication Interface with FIFO SCIF 557 14 1 Overview 557 14 1 1 Features 557 14 1 2 Block Diagrams 559 14 1 3 Pin Configuration 560 14 1 4 Register Configuration 561 14 2 Register Descriptions 562 14 2 1 Receive Shift Register SCRSR 562 14 2 2 Re...

Page 22: ...TDR 641 15 2 5 Serial Control Register SICTR 642 15 2 6 Serial Status Register SISTR 645 15 2 7 Receive Control Data Register SIRCDR 648 15 2 8 Transmit Control Data Register SITCDR 649 15 2 9 FIFO Control Register SIFCR 649 15 2 10 FIFO Data Count Register SIFDR 653 15 3 Operation 654 15 3 1 Input when TRMD 0 in SIFCR 654 15 3 2 Output when TRMD 0 in SIFCR 657 15 3 3 Output when TRMD 1 in SIFCR 6...

Page 23: ...01 17 2 6 Timer Counter TCNT 704 17 2 7 Timer General Register TGR 705 17 2 8 Timer Start Register TSTR 705 17 2 9 Timer Synchronous Register TSYR 706 17 3 Interface to Bus Master 707 17 3 1 16 Bit Registers 707 17 3 2 8 Bit Registers 707 17 4 Operation 709 17 4 1 Overview 709 17 4 2 Basic Functions 710 17 4 3 Synchronous Operation 716 17 4 4 Buffer Operation 718 17 4 5 PWM Modes 721 17 4 6 Phase ...

Page 24: ... 3 Data Register SDDR 758 18 3 4 Bypass Register SDBPR 758 18 3 5 Boundary scan register SDBSR 758 18 3 6 ID code register SDIDR 770 18 4 Operation 771 18 4 1 TAP Controller 771 18 4 2 H UDI Interrupt and Serial Transfer 772 18 4 3 H UDI Reset 775 18 5 Boundary Scan 775 18 5 1 Supported Instructions 775 18 5 2 Notes on Use 777 18 6 Usage Notes 777 Section 19 Pin Function Controller PFC 781 19 1 Ov...

Page 25: ...Canceling Standby Mode 807 21 4 3 Standby Mode Cancellation by NMI Interrupt 807 21 4 4 Clock Pause Function 808 21 4 5 Notes on Standby Mode 811 21 5 Module Standby Function 812 21 5 1 Transition to Module Standby Function 812 21 5 2 Clearing the Module Standby Function 812 Section 22 Electrical Characteristics 813 22 1 Absolute Maximum Ratings 813 22 2 DC Characteristics 814 22 3 AC Characterist...

Page 26: ...nd BUSHiZ Signal Timing 878 22 4 AC Characteristic Test Conditions 880 Appendix A On Chip Peripheral Module Registers 881 A 1 Addresses 881 Appendix B Pin States 900 B 1 Pin States in Reset Power Down State and Bus Released State 900 Appendix C Product Lineup 904 Appendix D Package Dimensions 905 ...

Page 27: ...n for applications such as realtime control which could not previously be handled by microcontrollers because of their high speed processing requirements The SH7616 also includes a maximum 4 kbyte cache for greater CPU processing power when accessing external memory The SH7616 is equipped with a media access controller MAC conforming to the IEEE802 3u standard and an Ethernet controller that inclu...

Page 28: ...uction set Fixed 16 bit instruction length for improved code efficiency Load store architecture basic operations are executed between registers Delayed branch instructions reduce pipeline disruption during branches C oriented instruction set Instruction execution time One instruction per cycle 16 0 ns instruction at 62 5 MHz operation Address space Architecture supports 4 Gbytes On chip multiplier...

Page 29: ...l registers DSP data bus Extended Harvard architecture Simultaneous access to two data buses and one instruction bus Parallel processing Maximum of four parallel processes ALU operations multiplication and two loads or stores Address processors Two address processors Address operations to access two memories DSP data addressing modes Increment and index Each with or without modulo addressing Repea...

Page 30: ...e writes in write back mode Interrupt controller INTC 16 priority levels can be set On chip supporting module interrupt vector numbers can be set 41 internal interrupt sources The E DMAC interrupt EINT is input to the INTC as the OR of 22 EtherC and E DMAC interrupt sources max Thus from the viewpoint of the INTC there is one EtherC E DMAC interrupt source Five external interrupt pins NMI IRL0 to ...

Page 31: ... channels C and D only bus master CPU DMAC bus cycle instruction fetch data access read write operand cycle byte word longword User break interrupt generated on occurrence of break condition Processing can be stopped before or after instruction execution in instruction fetch cycle Break with specification of number of executions channels C and D only Settable number of executions max 2 12 1 4095 P...

Page 32: ...back mode Refresh functions CAS before RAS refreshing auto refreshing or self refreshing Refresh interval settable by means of refresh counter and clock select setting Concentrated refreshing according to refresh count setting 1 2 4 6 8 Refresh request output possible REFOUT Direct DRAM interface Multiplexed row address column address output Fast page mode burst transfer and continuous access when...

Page 33: ... MHz Cycle stealing or burst transfer Relative channel priorities can be set fixed mode round robin mode DMA transfer is possible for the following devices External memory on chip memory on chip supporting modules excluding DMAC BSC UBC cache E DMAC EtherC External requests DMA transfer requests from on chip supporting modules auto requests Interrupt request DEIn can be issued to CPU at end of dat...

Page 34: ...with WOL Wake On LAN output CAM match signal input function Serial communi cation interface with FIFO SCIF 2 channels Asynchronous mode Data length 7 or 8 bits Stop bit length 1 or 2 Parity Even odd or none Receive error detection Parity errors framing errors overrun errors Break detection Synchronous mode One serial communication format 8 bit data length Receive error detection Overrun errors IrD...

Page 35: ...nd receive clocks Transmit and receive FIFO for primary data transmit and receive buffer for control data enabling continuous transmission reception Interval transfer mode and continuous transfer mode Choice of 8 or 16 bit data length Data transfer communication by means of polling or interrupts Choice of MSB or LSB first transfer for data I O Serial I O SIO 2 channels Full duplex operation indepe...

Page 36: ...r operation Counter clearing possible by compare match or input capture Synchronous operation Multiple timer counters TCNT can be written to simultaneously simultaneous clearing by compare match and input capture possible simultaneous register input output possible by counter synchronous operation PWM mode Any PWM output duty can be set maximum 7 phase PWM output possible by combination with synch...

Page 37: ...nput capture source ICI One overflow source OVI Watchdog timer WDT 1 channel Can be switched between watchdog timer mode and interval timer mode Internal reset external signal WDTOVF or interrupt generated on count overflow Used when standby mode is cleared or the clock frequency is changed and in clock pause mode Selection of eight counter input clocks Clock pulse generator CPG Built in clock pul...

Page 38: ...tings three power down modes Operating modes Control the method of clock generation PLL ON OFF and clock division ratio Power down mode Sleep mode CPU functions halted Standby mode All functions halted Module standby function Operation of FRT SCIF DMAC UBC DSP TPU and SIO on chip supporting modules is halted selectively I O ports 29 input output ports ...

Page 39: ...oller External bus interface Cache controller User debug interface Serial I O Timer pulse unit Watchdog timer Clock pulse generator Free running timer Serial communication interface with FIFO System controller Cache address bus Internal address bus Internal address bus Peripheral address bus Internal address bus 32 bit internal data bus 32 bit cache data bus 16 bit internal data bus 16 bit interna...

Page 40: ...VCC A7 A6 A5 A4 A3 A2 A1 VCC A0 VSS VSS D31 VCC D30 D29 D28 D27 D26 D25 VSS D24 VCC VCC D23 D22 D21 D20 VSS VSS D19 VCC D18 D17 D16 D15 D14 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181...

Page 41: ...l resonator EXTAL Input For connection to a crystal resonator or used as external clock input pin CKIO I O System clock input output pin Used as the external clock input or internal clock output pin CKPREQ CKM Input Clock pause request input Used as the clock pause request pin for changing the frequency of the clock input from the CKIO pin or halting the clock CKPACK Output Clock pause acknowledge...

Page 42: ...al device requests release of the bus Operating mode MD0 MD4 Input Mode setting The operating mode is specified by the levels at these pins Interrupts NMI Input Nonmaskable interrupt Inputs the nonmaskable interrupt request signal IRL3 IRL0 Input External interrupt request input 0 to 3 These pins input maskable interrupt request signals IVECF Output Interrupt vector fetch cycle Indicates an extern...

Page 43: ...utput Column address strobe 3 DRAM highest byte select signal CAS2 Output Column address strobe 2 DRAM second byte select signal CAS1 Output Column address strobe 1 DRAM third byte select signal CAS0 Output Column address strobe 0 DRAM lowest byte select signal CKE Output Clock enable Synchronous DRAM clock enable signal REFOUT Output Refresh out Signal requesting refresh execution when the bus is...

Page 44: ...t data 0 3 4 bit receive data TX ER Output Transmit error Signal sending error status to another port RX DV Input Receive data enable Indicates that enable receive data on ERXD0 3 exist ERXD0 3 Input Receive data 0 3 4 bit receive data RX ER Input Receive error Reports error state that occurred during transfer of frame data CRS Input Carrier sense Carrier detection notification signal COL Input Co...

Page 45: ...nication interface with TXD1 2 Output Transmit data output channel 1 2 SCIF channel 1 and 2 transmit data output pins FIFO SCIF RXD1 2 Input Receive data output channel 1 2 SCIF channel 1 and 2 receive data input pins SCK1 2 I O Serial clock input output channel 1 2 SCIF clock input output pins RTS Output Transmit request SCIF channel 1 transmit request output pin CTS Input Transmit enable SCIF ch...

Page 46: ...clock ports SRS0 Input Serial receive synchronization clock input 0 Serial receive synchronization input ports STXD0 Output Serial transmit data output 0 Serial data output ports STCK0 Input Serial transmit clock input 0 Serial transmit clock ports STS0 I O Serial transmit synchronization clock input output 0 Serial transmit synchronization input output ports Serial I O SIO SRXD1 2 Input Serial re...

Page 47: ...al input output port pins Input or output can be specified bit by bit Note PA3 cannot be used CKPO is valid instead 1 3 3 Pin Multiplexing Table 1 3 Pin Multiplexing No Function 1 Function 2 Function 3 Function 4 Type 12 PLLVCC Clocks 9 PLLVSS 11 PLLCAP1 10 PLLCAP2 19 EXTAL 21 XTAL 23 CKIO 24 CKPREQ CKM 25 CKPACK 9 pins 8 RES System control 13 MD4 14 MD3 15 MD2 16 MD1 17 MD0 6 pins 5 NMI Interrupt...

Page 48: ...tion 2 Function 3 Function 4 Type 131 BS Bus control 138 CS4 137 CS3 136 CS2 135 CS1 134 CS0 148 BGR 145 BRLS 115 WAIT 128 RD 117 RAS 118 CAS OE 119 DQMUU WE3 120 DQMUL WE2 121 DQMLU WE1 122 DQMLL WE0 123 CAS3 124 CAS2 125 CAS1 126 CAS0 127 CKE 129 REFOUT 133 RD WR 139 BUSHiZ 140 BH 25 pins ...

Page 49: ...J09B0292 0200 No Function 1 Function 2 Function 3 Function 4 Type 111 A24 Address bus 108 A23 107 A22 106 A21 105 A20 104 A19 103 A18 102 A17 100 A16 98 A15 97 A14 96 A13 95 A12 94 A11 93 A10 92 A9 90 A8 88 A7 87 A6 86 A5 85 A4 84 A3 83 A2 82 A1 80 A0 25 pins ...

Page 50: ...nction 1 Function 2 Function 3 Function 4 Type 77 D31 Data bus 75 D30 74 D29 73 D28 72 D27 71 D26 70 D25 68 D24 65 D23 64 D22 63 D21 62 D20 59 D19 57 D18 56 D17 55 D16 54 D15 53 D14 51 D13 49 D12 48 D11 47 D10 46 D9 44 D8 43 D7 41 D6 40 D5 39 D4 38 D3 37 D2 36 D1 34 D0 32 pins ...

Page 51: ...195 ERXD1 194 ERXD0 187 RX ER 190 CRS 189 COL 199 MDC 198 MDIO 18 pins 143 DACK1 DMAC 144 DACK0 141 DREQ1 142 DREQ0 4 pins Note When carrying out debugging using the E10A emulator this pin is used for mode switching It should be connected to VSS when using the E10A emulator ASE mode When using the chip in the normal user system and not using the E10A emulator user mode connect this pin to VCC When...

Page 52: ...RS1 RXD2 164 PB4 SRXD1 TXD2 165 PB3 STCK1 TIOCA0 166 PB2 STS1 TIOCB0 168 PB1 STXD1 TIOCC0 TCLKA 170 PB0 TIOCD0 TCLKB WOL 16 pins 171 PA13 SRCK0 Port A 172 PA12 SRS0 SIOF FRT WDT 173 PA11 SRXD0 EtherC 174 PA10 STCK0 5 V I O compatibility 175 PA9 STS0 176 PA8 STXD0 177 WDTOVF PA7 178 PA6 FTCI 180 PA5 FTI 182 PA4 FTOA 183 CKPO FTOB 184 PA2 LNKSTA 185 PA1 EXOUT 186 PA0 CAMSEN 14 pins Note Figures in s...

Page 53: ...or DMA address error NMI interrupt End of exception handling Bus request Exception Bus request cleared Bus request received Bus request cleared SLEEP instruction SBY 0 SLEEP instruction SBY 1 From any state when RES 0 and NMI 1 From any state when RES 0 and NMI 0 Reset states Power down state Note clock pause function Bus request received Bus request cleared RST 0 NMI 0 MSTP bit cleared MSTP bit s...

Page 54: ...begins program execution Subsequently the processing state is the program execution state Program Execution State In the program execution state the CPU executes program instructions in normal sequence Power Down State In the power down state the CPU stops operating to conserve power The power down state is entered by executing a SLEEP instruction The power down state includes two modes sleep mode...

Page 55: ...ip supporting module states and pin states are the same as in the normal standby mode entered by means of the SLEEP instruction A transition to the program execution state is made by applying a high level to the CKPREQ CKM pin In this mode the oscillator is halted greatly reducing power consumption Module Standby Function A module standby function is provided for the following on chip supporting m...

Page 56: ...ower on reset 4 Manual reset Standby mode Executing SLEEP instruction while SBY bit is set in SBYCR1 Halted Halted Halted and initialized 1 Held Undefined 1 NMI interrupt 2 Power on reset 3 Manual reset Module standby function Setting MSTP bit corresponding to individual module Operating Operating DSP halted Clock supply to specified module halted module initialized 2 Held Held 1 Clearing MSTP bit...

Page 57: ... R0 R15 which are 32 bits in length General registers are used for data processing and address calculation With SuperH microcomputer type instructions R0 is also used as an index register Several instructions are limited to use of R0 only R15 is used as the hardware stack pointer SP Saving and recovering the status register SR and program counter PC in exception processing is accomplished by refer...

Page 58: ...y the R0 functions as a source register or destination register R15 functions as a hardware stack pointer SP during exception processing Used as memory address registers memory index registers with DSP type instructions Notes 1 2 3 Figure 2 1 General Register Configuration With the assembler symbol names are used for R2 R3 R9 If it is wished to use a name that makes clear the role of a register fo...

Page 59: ...ssing mode and is used for such as on chip peripheral module register data transfers The VBR register functions as the base address of the exception processing vector area including interrupts The RS and RE registers are used for program repeat loop control The repeat count is designated in the SR register repeat counter RC the repeat start address in the RS register and the repeat end address in ...

Page 60: ...2 I1 I0 RF1 RF0 Q M DMX DMY 0000 0000 RC 31 28 27 16 15 12 11 10 9 8 7 4 3 2 1 0 Status register SR Repeat start register RS Repeat end register RE Global base register GBR Vector base register VBR Modulo register MOD ME Modulo end address MS Modulo start address 31 31 31 31 31 0 0 0 0 0 16 15 RS RE GBR VBR ME MS Figure 2 2 Control Register Configuration ...

Page 61: ...pt request mask I3 I0 Indicate the receive level of an interrupt request 0 to 15 3 2 Repeat flags RF1 RF0 Used in zero overhead repeat loop control Set as below for an SETRC instruction For 1 step repeat 00 RE RS 4 For 2 step repeat 01 RE RS 2 For 3 step repeat 11 RE RS 0 For 4 steps or more 10 RE RS 0 1 Saturation arithmetic bit S Used with MAC instructions and DSP instructions 1 Designates satur...

Page 62: ...registers consist of four 32 bit registers high and low multiply and accumulate registers MACH and MACL the procedure register PR and the program counter PC The MACH and MACL store the results of multiplication or multiply and accumulate operations The PR stores the return address from the subroutine procedure The PC indicates the address of the program in execution it controls the flow of the pro...

Page 63: ...he DSR register has bits that represent operation results a signed greater than bit GT a zero bit Z a negative value bit N an overflow bit V a DSP status bit DC DSP condition and a status selection bit CS condition select for controlling DC bit setting The DC bit represents one status flag and is very similar to the SuperH microprocessor CPU core T bit For conditional DSP type instructions DSP dat...

Page 64: ...Rev 2 00 Mar 09 2006 page 38 of 906 REJ09B0292 0200 39 32 31 0 A0G A1G A0 A1 M0 M1 X0 X1 Y0 Y1 DSP data registers DSP status register DSR GT Z N V CS 2 0 DC 8 7 6 5 4 3 2 1 0 31 Figure 2 4 DSP Register Configuration ...

Page 65: ...ivalence 5 Negative bit N Indicates that the operation result is negative or that operand 1 is smaller than operand 2 1 Operation result is negative or operand 1 is smaller 4 Overflow bit V Indicates that the operation result has overflowed 1 Operation result has overflowed 3 1 Status selection bits CS Designate the mode for selecting the operation result status set in the DC bit Do not set either...

Page 66: ...ection guard bits are always presupposed and each status flag is updated When place overflows occur so that the correct result cannot be displayed even when the guard bits are used the N flag cannot indicate the correct status 2 1 6 Initial Values of Registers Table 2 3 lists the values of the registers after reset Table 2 3 Initial Values of Registers Classification Register Initial Value General...

Page 67: ...oundary In such cases the access results cannot be guaranteed In particular the stack area referred to by the hardware stack pointer SP R15 stores the program counter PC and status register SR as longwords so establish the hardware stack pointer so that a 4n value will always result To enable sharing of the processor accessing memory in little endian mode and memory the CS2 4 space area 2 4 has a ...

Page 68: ...d point data format the integer data format and the logical data format The DSP type fixed point data format has a binary point fixed between bits 31 and 30 There are three types with guard bits without guard bits and multiplication input each with different valid bit lengths and value ranges The DSP type integer data format has a binary point fixed between bits 16 and 15 There are three types wit...

Page 69: ...ard bits Multiplication input With guard bits No guard bits Arithmetic shift PSHA Logical shift PSHL 39 39 39 39 32 32 31 31 31 31 31 31 31 31 31 22 21 0 0 0 0 0 0 0 0 0 28 to 28 2 31 1 to 1 2 31 1 to 1 2 15 223 to 223 1 215 to 215 1 32 to 32 16 to 16 231 to 231 1 16 15 16 16 16 16 16 15 15 15 15 15 Sign bit S Binary decimal point Unrelated to processing ignored 30 30 30 Figure 2 7 DSP Type Data F...

Page 70: ...and the guard bits of the A0 A1 registers are disregarded The upper word of the destination register is valid The lower word and the guard bits of the A0 A1 registers are cleared to 0 X Y Data Transfers The MOVX W and MOVY W instructions access X Y memory via the 16 bit X Y data buses The data loaded into registers and data stored from registers is always the upper word the upper 16 bits bits 31 1...

Page 71: ...e not zero cleared but retain their previous values If the DSP registers are used as source registers in longword mode when data is stored from any registers other than A0G A1G the 32 bits data of the register are transferred When the A0 A1 registers are used as the source registers the guard bits are disregarded When the A0G A1G registers are the source registers in longword mode only 8 bits of t...

Page 72: ...peration Fixed decimal PDMSB PSHA 40 bit data Integer 24 bit data Logic PSHL PMULS 16 bit data Data transfer MOVX W MOVY W MOVS W MOVS L 32 bit data A0G A1G Data MOVS W Data transfer MOVS L X0 X1 Y0 Y1 M0 M1 DSP operation Fixed decimal PDMSB PSHA Sign 32 bit data Integer 16 bit data Logic PSHL PMULS Data MOVS W transfer MOVS L 32 bit data Note The sign is extended and stored in the ALU s guard bit...

Page 73: ...ixed decimal PSHA PMULS Sign extend 40 bit result Integer PDMSB 24 bit result Clear to 0 Logic PSHL Clear to 0 16 bit result Data transfer MOVS W Sign extend MOVS L 32 bit data A0G A1G Data transfer MOVS W Data Not updated Not updated MOVS L X0 X1 Y0 Y1 M0 M1 DSP operation Fixed decimal PSHA PMULS 32 bit result Integer logic PDMSB PSHL 16 bit result Clear to 0 Data transfer MOVX W MOVY W MOVS W MO...

Page 74: ...lows 16 Bit Fixed Length All instructions are 16 bits long increasing program code efficiency One Instruction per Cycle The microprocessor can execute basic instructions in one cycle using the pipeline system One state equals 16 0 ns when operating at 62 5 MHz Data Length Longword is the basic data length for all operations Memory can be accessed in bytes words or longwords Byte or word data acces...

Page 75: ...delayed branch instruction slot instruction This reduces pipeline disruption during branching The branching operation of the delayed branch occurs after execution of the slot instruction However with the exception of such branch operations as register updating execution of instructions is performed with the order of delayed branch instruction then delayed slot instruction For example even if the c...

Page 76: ...0 BGE TRGET0 BLT TRGET1 ADD 1 R0 CMP EQ 0 R0 BT TRGET T bit is not changed by ADD T bit is set when R0 0 The program branches when R0 0 SUB W 1 R0 BEQ TRGET Immediate Data Byte immediate data resides in instruction code Word or longword immediate data is not input in instruction codes but is stored in a memory table An immediate data transfer instruction MOV accesses the memory table using the PC ...

Page 77: ...SH7616 CPU Example of Conventional CPU Absolute address MOV L disp PC R1 MOV B R1 R0 DATA L H 12345678 MOV B H 12345678 R0 16 Bit 32 Bit Displacement When data is accessed by 16 bit or 32 bit displacement the pre existing displacement value is placed in the memory table Loading the immediate data when the instruction is executed transfers that value to the register and the data is accessed in the ...

Page 78: ...fective address is the content of register Rn Rn Rn Rn Post increment indirect register addressing Rn The effective address is the content of register Rn A constant is added to the content of Rn after the instruction is executed 1 is added for a byte operation 2 for a word operation and 4 for a longword operation Rn Rn 1 2 4 Rn 1 2 4 Rn After the instruction executes Byte Rn 1 Rn Word Rn 2 Rn Long...

Page 79: ...r a longword operation Rn 1 2 4 disp zero extended Rn disp 1 2 4 Byte Rn disp Word Rn disp 2 Longword Rn disp 4 Indirect indexed register addressing R0 Rn The effective address is the Rn value plus R0 Rn R0 Rn R0 Rn R0 Indirect GBR addressing with displacement disp 8 GBR The effective address is the GBR value plus an 8 bit displacement disp The value of disp is zero extended and remains the same f...

Page 80: ...R R0 GBR R0 PC relative addressing with displacement disp 8 PC The effective address is the PC value plus an 8 bit displacement disp The value of disp is zero extended is doubled for a word operation and is quadrupled for a longword operation For a longword operation the lowest two bits of the PC value are masked PC H FFFFFFFC 2 4 for longword disp zero extended PC disp 2 or PC H FFFFFFFC disp 4 W...

Page 81: ...e sign extended with a 12 bit displacement disp doubled and added to the PC value PC 2 disp sign extended PC disp 2 PC disp 2 Rn The effective address is the register PC value plus Rn PC Rn PC Rn PC Rn Immediate addressing imm 8 The 8 bit immediate data imm for the TST AND OR and XOR instructions are zero extended imm 8 The 8 bit immediate data imm for the MOV ADD and CMP EQ instructions are sign ...

Page 82: ...t word 16 bit 32 bit word longword Bus contention None Yes Memory X Y data memory All memory spaces Source registers Dx Dy A0 A1 Ds A0 A1 M0 M1 X0 X1 Y0 Y1 A0G A1G Destination registers Dx X0 X1 Dy Y0 Y1 Ds A0 A1 M0 M1 X0 X1 Y0 Y1 A0G A1G X Y Data Addressing Among the DSP instructions the MOVX W and MOVY W instructions can be used to simultaneously access X Y data memory The DSP instructions have ...

Page 83: ...the index register and designate add index register addressing During X Y data addressing only bits 1 to 15 of the address pointer are valid Always write a 0 to bit 0 of the address pointer and the index register during X Y data addressing Figure 2 9 shows the X Y data transfer addressing When X memory and Y memory are accessed using the X Y bus the upper word of Ax R4 or R5 and Ay R6 or R7 is ign...

Page 84: ...Is register values are added to them after the data transfer post update 3 Increment address registers The As registers are address pointers The value 2 or 4 is added after the data transfer post update 4 Decrement address registers The As registers are address pointers The value 2 or 4 is added 2 or 4 is subtracted before the data transfer pre update The address pointer As uses the R8 register as...

Page 85: ... modulo addressing mode at the same time Therefore do not simultaneously set the DMX and DMY If they happen to be set at the same time only the DMY side is valid The MOD register is used to designate the start and end addresses of the modulo address area it stores the MS modulo start and ME modulo end An example of MOD register MS ME usage is indicated below MOV L ModAddr Rn Rn ModEnd ModStart LDC...

Page 86: ...Inc R4 H 1000E00C Inc R4 H 1000E008 becomes the modulo start address because the modulo end address occurred Data is placed so that the upper 16 bits of the modulo start and end addresses become identical This is so because the modulo start address replaces only the lower 15 bits of the address register excepting bit 0 Note When using add index with DSP data addressing there are cases where the va...

Page 87: ... Ix Ay is one of R6 7 if DMY 0 Ay Ay 2 or R9 Iy or 0 Inc Index Not Update else if not update Ay modulo Ay 2 or R9 Iy else if Operation is MOVS W or MOVS L if Addressing is Nop Inc Add index reg MAB As memory access cycle uses MAB The address to be used has not been updated As is one of R2 5 As As 2 or 4 or R8 Is or 0 Inc Index Not Update else Decrement Pre update As is one of R2 5 As As 2 or 4 MAB...

Page 88: ...AddrReg 2 4 3 Instruction Formats for CPU Instructions The instruction format of instructions executed by the CPU core and the meanings of the source and destination operands are indicated below The meaning of the operand depends on the instruction code The symbols are used as follows xxxx Instruction code mmmm Source register nnnn Destination register iiii Immediate data dddd Displacement ...

Page 89: ... nnnn 15 0 nnnn Direct register MOVT Rn Control register or system register nnnn Direct register STS MACH Rn Control register or system register nnnn Indirect pre decrement register STC L SR Rn m format xxxx mmmm xxxx xxxx 15 0 mmmm Direct register Control register or system register LDC Rm SR mmmm Indirect post increment register Control register or system register LDC L Rm SR mmmm Indirect regis...

Page 90: ...ost increment register nnnn Direct register MOV L Rm Rn mmmm Direct register nnnn Indirect pre decrement register MOV L Rm Rn mmmm Direct register nnnn Indirect indexed register MOV L Rm R0 Rn md format xxxx dddd 15 0 mmmm xxxx mmmmdddd indirect register with displacement R0 Direct register MOV B disp Rm R0 nd4 format dddd nnnn xxxx 15 0 xxxx R0 Direct register nnnndddd Indirect register with disp...

Page 91: ...OVA disp PC R0 dddddddd PC relative BF label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd PC relative BRA label label disp PC nd8 format dddd nnnn xxxx 15 0 dddd dddddddd PC relative with displacement nnnn Direct register MOV L disp PC Rn i format iiiiiiii Immediate Indirect indexed GBR AND B imm R0 GBR i i i i xxxx 15 0 xxxx i i i i iiiiiiii Immediate R0 Direct register AND imm R0 iiiiiiii Im...

Page 92: ...SP unit 32 bit length Figure 2 12 shows each of the instruction formats CPU core instructions 0 0 0 0 to 1 1 1 0 Double data transfer instructions Single data transfer instructions Parallel processing instructions B field A field A field A field 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 15 15 15 15 0 0 0 0 31 10 10 9 9 16 26 25 Figure 2 12 Instruction Formats for DSP Instructions Double Single Data Tran...

Page 93: ...0 0 0 data transfers MOVY W Ay Dy MOVY W Ay Dy MOVY W Ay Iy Dy Ay MOVY W Da Ay MOVY W Da Ay MOVY W Da Ay Iy Category Mnemonic 7 6 5 4 3 2 1 0 X memory NOPX 0 0 0 0 data transfers MOVX W Ax Dx MOVX W Ax Dx MOVX W Ax Ix Dx Dx 0 0 1 1 1 0 1 MOVX W Da Ax MOVX W Da Ax MOVX W Da Ax Ix Da 1 0 1 1 1 0 1 Y memory NOPY 0 0 0 0 data transfers MOVY W Ay Dy MOVY W Ay Dy MOVY W Ay Iy Dy Dy 0 0 1 1 1 0 1 MOVY W ...

Page 94: ...s MOVS L As Ds MOVS L As Ds MOVS L As Is Ds MOVS L Ds As MOVS L Ds As MOVS L Ds As MOVS L Ds As Is Category Mnemonic 7 6 5 4 3 2 1 0 Single data transfer MOVS W As Ds MOVS W As Ds MOVS W As Ds MOVS W As Is Ds Ds 0 1 2 3 0 0 1 1 0 1 0 1 0 0 MOVS W Ds As MOVS W Ds As MOVS W Ds As MOVS W Ds As Is 4 5 A1 6 7 A0 0 0 1 1 0 1 0 1 1 MOVS L As Ds MOVS L As Ds MOVS L As Ds MOVS L As Is Ds 8 X0 9 X1 A Y0 B Y...

Page 95: ...ions These instructions can be defined independently the processes can be independent and furthermore they can be executed simultaneously in parallel Table 2 17 indicates the A field parallel data transfer instructions and table 2 18 indicates the B field ALU operation instructions and multiplication instructions A fields instruction is the same as double data transfers in table 2 15 Table 2 17 A ...

Page 96: ...a transfers MOVX W Ax Dx MOVX W Ax Dx MOVX W Ax Ix Dx 0 0 1 1 1 0 1 MOVX W Da Ax MOVX W Da Ax MOVX W Da Ax Ix 1 0 1 1 1 0 1 Y memory NOPY 0 0 0 0 data transfers MOVY W Ay Dy MOVY W Ay Dy MOVY W Ay Iy Dy Dy 0 0 1 1 1 0 1 MOVY W Da Ay MOVY W Da Ay MOVY W Da Ay Iy Da 1 0 1 1 1 0 1 Ax 0 R4 1 R5 Ay 0 R6 1 R7 Dx 0 X0 1 X1 Dy 0 Y0 1 Y1 Da 0 A0 1 A1 ...

Page 97: ... 1 E M1 F 1 0 0 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 1 1 1 0 X0 1 X1 2 Y0 3 A1 0 X0 1 X1 2 A0 3 A1 0 X0 0 Y0 1 Y1 2 X0 3 A1 0 Y0 0 M0 1 Y0 1 Y1 1 M1 2 A0 2 M0 2 A0 3 A1 3 M1 3 A1 0 1 0 PSHL lmm Dz PSHA lmm Dz PMULS Se Sf Dg Reserved Reserved Reserved Reserved Reserved Reserved PABS Sx Dz PRND Sx Dz PRND Sy Dz PABS Sy Dz Reserved PSUBC Sx Sy Dz PADDC Sx Sy Dz PCMP Sx Sy...

Page 98: ...x Dz if cc PDMSB Sy Dz if cc PNEG Sx Dz if cc PNEG Sy Dz if cc PCOPY Sx Dz if cc PCOPY Sy Dz if cc PSTS MACH Dz if cc PSTS MACL Dz if cc PLDS Dz MACL if cc PLDS Dz MACH Conditional three operand instructions 0 0 if cc 10 DCT 11 DCF 01 Uncon dition 31 27 25 16 26 1 11 1 0 A field Notes 1 System reserved code 2 if cc DCT DC bit true DCF DC bit false or none unconditional instruction Don t care 2 5 I...

Page 99: ... registers connected Arithmetic 21 ADD Binary addition 33 operations ADDC Binary addition with carry ADDV Binary addition with overflow CMP cond Comparison DIV1 Division DIV0S Initialization of signed division DIV0U Initialization of unsigned division DMULS Signed double length multiplication DMULU Unsigned double length multiplication DT Decrement and test EXTS Sign extension EXTU Zero extension ...

Page 100: ... ROTR One bit right rotation SHAL One bit arithmetic left shift SHAR One bit arithmetic right shift SHLL One bit logical left shift SHLLn n bit logical left shift SHLR One bit logical right shift SHLRn n bit logical right shift Branch 9 BF Conditional branch conditional branch with delay Branch when T 0 11 BT Conditional branch conditional branch with delay Branch when T 1 BRA Unconditional branch...

Page 101: ...LRT T bit clear LDC Load to control register LDRE Load to repeat end register LDRS Load to repeat start register LDS Load to system register NOP No operation RTE Return from exception processing SETRC Repeat count setting SETT T bit set SLEEP Shift into power down mode STC Storing control register data STS Storing system register data TRAPA Trap exception handling Total 65 182 ...

Page 102: ...ndicates summary of operation Explanation of Symbols Transfer direction xx Memory operand M Q T Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n n bit left shift n n bit right shift Value when no wait states are inserted 1 Value of T bit after instruction is executed Explanation of Symbols No change Notes 1 Instruction execution ...

Page 103: ...extension Rn 1 MOV L Rm Rn 0110nnnnmmmm0010 Rm Rn 1 MOV B Rm Rn 0010nnnnmmmm0100 Rn 1 Rn Rm Rn 1 MOV W Rm Rn 0010nnnnmmmm0101 Rn 2 Rn Rm Rn 1 MOV L Rm Rn 0010nnnnmmmm0110 Rn 4 Rn Rm Rn 1 MOV B Rm Rn 0110nnnnmmmm0100 Rm Sign extension Rn Rm 1 Rm 1 MOV W Rm Rn 0110nnnnmmmm0101 Rm Sign extension Rn Rm 2 Rm 1 MOV L Rm Rn 0110nnnnmmmm0110 Rm Rn Rm 4 Rm 1 MOV B R0 disp Rn 10000000nnnndddd R0 disp Rn 1 M...

Page 104: ...disp GBR 1 MOV W R0 disp GBR 11000001dddddddd R0 disp 2 GBR 1 MOV L R0 disp GBR 11000010dddddddd R0 disp 4 GBR 1 MOV B disp GBR R0 11000100dddddddd disp GBR Sign extension R0 1 MOV W disp GBR R0 11000101dddddddd disp 2 GBR Sign extension R0 1 MOV L disp GBR R0 11000110dddddddd disp 4 GBR R0 1 MOVA disp PC R0 11000111dddddddd disp 4 PC R0 1 MOVT Rn 0000nnnn00101001 T Rn 1 SWAP B Rm Rn 0110nnnnmmmm1...

Page 105: ...010 If Rn Rm with unsigned data 1 T 1 Comparison result CMP GE Rm Rn 0011nnnnmmmm0011 If Rn Rm with signed data 1 T 1 Comparison result CMP HI Rm Rn 0011nnnnmmmm0110 If Rn Rm with unsigned data 1 T 1 Comparison result CMP GT Rm Rn 0011nnnnmmmm0111 If Rn Rm with signed data 1 T 1 Comparison result CMP PL Rn 0100nnnn00010101 If Rn 0 1 T 1 Comparison result CMP PZ Rn 0100nnnn00010001 If Rn 0 1 T 1 Co...

Page 106: ...0nnnnmmmm1111 A word in Rm is sign extended Rn 1 EXTU B Rm Rn 0110nnnnmmmm1100 A byte in Rm is zero extended Rn 1 EXTU W Rm Rn 0110nnnnmmmm1101 A word in Rm is zero extended Rn 1 MAC L Rm Rn 0000nnnnmmmm1111 Signed operation of Rn Rm MAC MAC 32 32 64 64 bits 3 2 to 4 MAC W Rm Rn 0100nnnnmmmm1111 Signed operation of Rn Rm MAC MAC 16 16 64 64 bits 3 2 MUL L Rm Rn 0000nnnnmmmm0111 Rn Rm MACL 32 32 32...

Page 107: ...les T Bit AND Rm Rn 0010nnnnmmmm1001 Rn Rm Rn 1 AND imm R0 11001001iiiiiiii R0 imm R0 1 AND B imm R0 GBR 11001101iiiiiiii R0 GBR imm R0 GBR 3 NOT Rm Rn 0110nnnnmmmm0111 Rm Rn 1 OR Rm Rn 0010nnnnmmmm1011 Rn Rm Rn 1 OR imm R0 11001011iiiiiiii R0 imm R0 1 OR B imm R0 GBR 11001111iiiiiiii R0 GBR imm R0 GBR 3 TAS B Rn 0100nnnn00011011 If Rn is 0 1 T 1 MSB of Rn 4 Test result TST Rm Rn 0010nnnnmmmm1000 ...

Page 108: ...00nnnn00100100 T Rn T 1 MSB ROTCR Rn 0100nnnn00100101 T Rn T 1 LSB SHAL Rn 0100nnnn00100000 T Rn 0 1 MSB SHAR Rn 0100nnnn00100001 MSB Rn T 1 LSB SHLL Rn 0100nnnn00000000 T Rn 0 1 MSB SHLR Rn 0100nnnn00000001 0 Rn T 1 LSB SHLL2 Rn 0100nnnn00001000 Rn 2 Rn 1 SHLR2 Rn 0100nnnn00001001 Rn 2 Rn 1 SHLL8 Rn 0100nnnn00011000 Rn 8 Rn 1 SHLR8 Rn 0100nnnn00011001 Rn 8 Rn 1 SHLL16 Rn 0100nnnn00101000 Rn 16 Rn...

Page 109: ... 1 disp 2 PC PC if T 0 nop 3 1 BT S label 10001101dddddddd Delayed branch if T 1 disp 2 PC PC if T 0 nop 2 1 BRA label 1010dddddddddddd Delayed branch disp 2 PC PC 2 BRAF Rm 0000mmmm00100011 Delayed branch Rm PC PC 2 BSR label 1011dddddddddddd Delayed branch PC PR disp 2 PC PC 2 BSRF Rm 0000mmmm00000011 Delayed branch PC PR Rm PC PC 2 JMP Rm 0100mmmm00101011 Delayed branch Rm PC 2 JSR Rm 0100mmmm0...

Page 110: ... LDC L Rm VBR 0100mmmm00100111 Rm VBR Rm 4 Rm 3 LDC L Rm MOD 0100mmmm01010111 Rm MOD Rm 4 Rm 3 LDC L Rm RE 0100mmmm01110111 Rm RE Rm 4 Rm 3 LDC L Rm RS 0100mmmm01100111 Rm RS Rm 4 Rm 3 LDRE disp PC 10001110dddddddd disp 2 PC RE 1 LDRS disp PC 10001100dddddddd disp 2 PC RS 1 LDS Rm MACH 0100mmmm00001010 Rm MACH 1 LDS Rm MACL 0100mmmm00011010 Rm MACL 1 LDS Rm PR 0100mmmm00101010 Rm PR 1 LDS Rm DSR 0...

Page 111: ... operation result repeat status RF1 RF0 Rm 11 0 RC SR 27 16 1 SETRC imm 10000010iiiiiiii RE RS operation result repeat status RF1 RF0 imm RC SR 23 16 0 SR 27 24 1 1 SETT 0000000000011000 1 T 1 1 SLEEP 0000000000011011 Sleep 3 STC SR Rn 0000nnnn00000010 SR Rn 1 STC GBR Rn 0000nnnn00010010 GBR Rn 1 STC VBR Rn 0000nnnn00100010 VBR Rn 1 STC MOD Rn 0000nnnn01010010 MOD Rn 1 STC RE Rn 0000nnnn01110010 R...

Page 112: ...0101010 Y0 Rn 1 STS Y1 Rn 0000nnnn10111010 Y1 Rn 1 STS L MACH Rn 0100nnnn00000010 Rn 4 Rn MACH Rn 1 STS L MACL Rn 0100nnnn00010010 Rn 4 Rn MACL Rn 1 STS L PR Rn 0100nnnn00100010 Rn 4 Rn PR Rn 1 STS L DSR Rn 0100nnnn01100010 Rn 4 Rn DSR Rn 1 STS L A0 Rn 0100nnnn01110010 Rn 4 Rn A0 Rn 1 STS L X0 Rn 0100nnnn10000010 Rn 4 Rn X0 Rn 1 STS L X1 Rn 0100nnnn10010010 Rn 4 Rn X1 Rn 1 STS L Y0 Rn 0100nnnn1010...

Page 113: ...been added to the status register SR The LDC and STC instructions have been added in order to access the aforementioned The LDS and STS instructions have been added in order to access the DSP registers DSR A0 X0 X1 Y0 and Y1 The SETRC instruction has been added to set the repeat counter RC bits 27 to 16 and repeat flags RF1 RF0 bits 3 and 2 of the SR register When the SETRC instruction operand is ...

Page 114: ... 0100nnnn01100011 Rn 4 Rn RS Rn 2 LDS Rm DSR 0100mmmm01101010 Rm DSR 1 LDS L Rm DSR 0100mmmm01100110 Rm DSR Rm 4 Rm 1 LDS Rm A0 0100mmmm01111010 Rm A0 1 LDS L Rm A0 0100mmmm01110110 Rm A0 Rm 4 Rm 1 LDS Rm X0 0100mmmm10001010 Rm X0 1 LDS L Rm X0 0100mmmm10000110 Rm X0 Rm 4 Rm 1 LDS Rm X1 0100mmmm10011010 Rm X1 1 LDS L Rm X1 0100mmmm10010110 Rm X1 Rm 4 Rm 1 LDS Rm Y0 0100mmmm10101010 Rm Y0 1 LDS L R...

Page 115: ...unction No of Instructions 4 NOPX X memory no operation 14 MOVX X memory data transfer Double datatransferinstr uctions NOPY Y memory no operation MOVY Y memory data transfer Single data transfer instructions 1 MOVS Single data transfer 16 Total 5 Total 30 The data transfer instructions are divided into two groups double data transfers and single data transfers Double data transfers can be combine...

Page 116: ... of Dx 0 LSW of Dx Ax 2 Ax 111100A D 0 10 1 MOVX W Ax Ix Dx Ax MSW of Dx 0 LSW of Dx Ax Ix Ax 111100A D 0 11 1 MOVX W Da Ax MSW of Da Ax 111100A D 1 01 1 MOVX W Da Ax MSW of Da Ax Ax 2 Ax 111100A D 1 10 1 MOVX W Da Ax Ix MSW of Da Ax Ax Ix Ax 111100A D 1 11 1 Table 2 29 Double Data Transfer Instructions Y Memory Data Instruction Operation Code Cycles DC Bit NOPY No Operation 111100 0 0 0 00 1 MOVY...

Page 117: ...DDD0001 1 MOVS W Ds As MSW of Ds As 111101AADDDD0101 1 MOVS W Ds As MSW of Ds As As 2 As 111101AADDDD1001 1 MOVS W Ds As Is MSW of Ds As As Is As 111101AADDDD1101 1 MOVS L As Ds As 4 As As Ds 111101AADDDD0010 1 MOVS L As Ds As Ds 111101AADDDD0110 1 MOVS L As Ds As Ds As 4 As 111101AADDDD1010 1 MOVS L As Is Ds As Ds As Is As 111101AADDDD1110 1 MOVS L Ds As As 4 As Ds As 111101AADDDD0011 1 MOVS L Ds...

Page 118: ... 2 31 Correspondence between DSP Data Transfer Operands and Registers SH CPU Core Registers Oper and R0 R1 R2 As2 R3 As3 R4 Ax0 As0 R5 Ax1 As0 R6 Ay0 R7 Ay1 R8 Ix Is R9 Iy Ax Yes Yes Ix Is Yes Dx Ay Yes Yes Iy Yes Dy Da As Yes Yes Yes Yes Ds Oper DSP Registers and X0 X1 Y0 Y1 M0 M1 A0 A1 A0G A1G Ax Ix Is Dx Yes Yes Ay Iy Dy Yes Yes Da Yes Yes As Ds Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Note Yes ...

Page 119: ...tion instructions and unconditional single data operation instructions Table 2 32 lists the instruction formats of the DSP operation instructions Each of the operands can be independently selected from the DSP registers Table 2 33 shows the correspondence between the DSP operation instruction operands and registers Table 2 32 DSP Operation Instruction Formats Classification Instruction Forms Instr...

Page 120: ... A0 R5 R8 MOVY W R7 Y0 PCMP X1 M0 MOVX W R4 R8 NOPY Text in brackets can be omitted The no operation instructions NOPX and NOPY can be omitted Semicolons are used to demarcate instruction lines but can be omitted If semicolons are used the space after the semicolon can be used for comments The individual status codes DC N Z V GT of the DSR register are always updated by unconditional ALU operation...

Page 121: ...btraction PSUB PMULS Subtraction and signed multiplication PSUBC Subtraction with borrow ALU integer operation 2 PDEC Decrement 12 instructions PINC Increment MSB detection instruction 1 PDMSB MSB detection 6 Rounding operation instruction 1 PRND Rounding 2 ALU logical operation 3 PAND Logical AND 9 instructions POR Logical OR PXOR Logical exclusive OR Fixed decimal point multiplication instructio...

Page 122: ...DD Sx Sy Dz if DC 1 Sx Sy Dz if 0 nop 111110 10110010xxyyzzzz 1 DCF PADD Sx Sy Dz if DC 0 Sx Sy Dz if 1 nop 111110 10110011xxyyzzzz 1 PADD Sx Sy Du PMULS Se Sf Dg Sx Sy Du MSW of Se MSW of Sf Dg 111110 0111eeffxxyygguu 1 Update PADDC Sx Sy Dz Sx Sy DC Dz 111110 10110000xxyyzzzz 1 Update PCLR Dz H 00000000 Dz 111110 100011010000zzzz 1 Update DCT PCLR Dz if DC 1 H 00000000 Dz if 0 nop 111110 1000111...

Page 123: ... PNEG Sx Dz if DC 1 0 Sx Dz if 0 nop 111110 11001010xx00zzzz 1 DCT PNEG Sy Dz if DC 1 0 Sy Dz if 0 nop 111110 1110101000yyzzzz 1 DCF PNEG Sx Dz if DC 0 0 Sx Dz if 1 nop 111110 11001011xx00zzzz 1 DCF PNEG Sy Dz if DC 0 0 Sy Dz if 1 nop 111110 1110101100yyzzzz 1 PSUB Sx Sy Dz Sx Sy Dz 111110 10100001xxyyzzzz 1 Update DCT PSUB Sx Sy Dz if DC 1 Sx Sy Dz if 0 nop 111110 10100010xxyyzzzz 1 DCF PSUB Sx S...

Page 124: ... If DC 0 MSW of Sx 1 MSW of Dz clear LSW of Dz if 1 nop 111110 10001011xx00zzzz 1 DCF PDEC Sy Dz If DC 0 MSW of Sy 1 MSW of Dz clear LSW of Dz if 1 nop 111110 1010101100yyzzzz 1 PINC Sx Dz MSW of Sx 1 MSW of Dz clear LSW of Dz 111110 10011001xx00zzzz 1 Update PINC Sy Dz MSW of Sy 1 MSW of Dz clear LSW of Dz 111110 1011100100yyzzzz 1 Update DCT PINC Sx Dz If DC 1 MSW of Sx 1 MSW of Dz clear LSW of ...

Page 125: ...of Dz if 0 nop 111110 10011110xx00zzzz 1 DCT PDMSB Sy Dz If DC 1 Sy data MSB position MSW of Dz clear LSW of Dz if 0 nop 111110 1011111000yyzzzz 1 DCF PDMSB Sx Dz If DC 0 Sx data MSB position MSW of Dz clear LSW of Dz if 1 nop 111110 10011111xx00zzzz 1 DCF PDMSB Sy Dz If DC 0 Sy data MSB position MSW of Dz clear LSW of Dz if 1 nop 111110 1011111100yyzzzz 1 Table 2 38 Rounding Operation Instruction...

Page 126: ...z clear LSW of Dz 111110 10110101xxyyzzzz 1 Update DCT POR Sx Sy Dz If DC 1 Sx Sy Dz clear LSW of Dz if 0 nop 111110 10110110xxyyzzzz 1 DCF POR Sx Sy Dz If DC 0 Sx Sy Dz clear LSW of Dz if 1 nop 111110 10110111xxyyzzzz 1 PXOR Sx Sy Dz Sx Sy Dz clear LSW of Dz 111110 10100101xxyyzzzz 1 Update DCT PXOR Sx Sy Dz If DC 1 Sx Sy Dz clear LSW of Dz if 0 nop 111110 10100110xxyyzzzz 1 DCF PXOR Sx Sy Dz If ...

Page 127: ...SHA Sx Sy Dz if Sy 0 Sx Sy Dz if Sy 0 Sx Sy Dz 111110 10010001xxyyzzzz 1 Update DCT PSHA Sx Sy Dz if DC 1 Sy 0 Sx Sy Dz if DC 1 Sy 0 Sx Sy Dz if DC 0 nop 111110 10010010xxyyzzzz 1 DCF PSHA Sx Sy Dz if DC 0 Sy 0 Sx Sy Dz if DC 0 Sy 0 Sx Sy Dz if DC 1 nop 111110 10010011xxyyzzzz 1 PSHA imm Dz if imm 0 Dz imm Dz if imm 0 Dz imm Dz 111110 00010iiiiiiizzzz 1 Update ...

Page 128: ...ar LSW of Dz 111110 10000001xxyyzzzz 1 Update DCT PSHL Sx Sy Dz if DC 1 Sy 0 Sx Sy Dz clear LSW of Dz if DC 1 Sy 0 Sx Sy Dz clear LSW of Dz if DC 0 nop 111110 10000010xxyyzzzz 1 DCF PSHL Sx Sy Dz if DC 0 Sy 0 Sx Sy Dz clear LSW of Dz if DC 0 Sy 0 Sx Sy Dz clear LSW of Dz if DC 1 nop 111110 10000011xxyyzzzz 1 PSHL imm Dz if imm 0 Dz imm Dz clear LSW of Dz if imm 0 Dz imm Dz clear LSW of Dz 111110 0...

Page 129: ...ACL if 0 nop 111110 111111100000zzzz 1 DCF PLDS Dz MACH if DC 0 Dz MACH if 1 nop 111110 111011110000zzzz 1 DCF PLDS Dz MACL if DC 0 Dz MACL if 1 nop 111110 111111110000zzzz 1 PSTS MACH Dz MACH Dz 111110 110011010000zzzz 1 PSTS MACL Dz MACL Dz 111110 110111010000zzzz 1 DCT PSTS MACH Dz if DC 1 MACH Dz if 0 nop 111110 110011100000zzzz 1 DCT PSTS MACL Dz if DC 1 MACL Dz if 0 nop 111110 110111100000zz...

Page 130: ...d NOPY instruction codes Table 2 44 NOPX and NOPY Instruction Codes Instruction Code PADD X0 Y0 A0 MOVX W R4 X0 MOVY W R6 R9 Y0 1111100000001011 1011000100000111 PADD X0 Y0 A0 NOPX MOVY W R6 R9 Y0 1111100000000011 1011000100000111 PADD X0 Y0 A0 NOPX NOPY 1111100000000000 1011000100000111 PADD X0 Y0 A0 NOPX 1111100000000000 1011000100000111 PADD X0 Y0 A0 1111100000000000 1011000100000111 MOVX W R4 ...

Page 131: ... the following instruction strings in the order of a b and c a Double precision multiplication MUL L DMULU L DMULS L or double precision product sum operation MAC L b DSP computing instruction excluding PMULS PSTS and PLDS c Execution of PMLS PSTS or PLDS instruction The above caution also applies when there is a delayed jump instruction immediately before the above 2 a and the instruction 2 a is ...

Page 132: ...Section 2 CPU Rev 2 00 Mar 09 2006 page 106 of 906 REJ09B0292 0200 ...

Page 133: ...odes 3 2 1 Clock Pulse Generator A block diagram of the on chip clock pulse generator circuit is shown in figure 3 1 CAP1 CKIO MD2 MD0 MD1 CKPACK Oscillator On Off PLL circuit 1 PLL circuit 2 1 2 4 CAP2 EXTAL XTAL CKPREQ CKM Clock mode control circuit DIVP 1 1 1 2 1 4 Note See section 21 4 4 Clock Pause Function Eφ External interface clock Iφ CPU DSP core clock Pφ Peripheral module clock The relat...

Page 134: ...pins specifies the clock mode MD1 I MD2 I CKPREQ CKM I Used as the clock pause request pin or specifies operation of the crystal resonator CKPACK O Clock pause function PLL Circuit 1 PLL circuit 1 eliminates phase differences between external clocks and clocks supplied internally within the chip In high speed operation the phase difference between the reference clocks and operating clocks in the c...

Page 135: ...requency modification register FMR The CKIO pin can also be placed in the high impedance state However clock phase shifting is not performed when PLL circuit 1 is halted Normally mode 0 should be used 2 Only PLL circuit 2 operates The clock from PLL circuit 2 is output from the CKIO pin having the same frequency as the Eφ As PLL circuit 1 does not operate phases are not matched in this mode PLL ci...

Page 136: ... clock phase shifting is not performed when PLL circuit 1 is halted Normally mode 4 should be used External clock input 6 PLL circuits 1 and 2 do not operate Set this mode when a clock having a frequency equal to that of clocks the clock input from the CKIO pin is used The internal clock frequency can be changed in each clock mode see section 3 2 5 Operating Frequency Selection by Register In cloc...

Page 137: ...on impedance 1 0 0 1 0 Clock input Open Output high 1 Crystal oscillation Crystal oscillation impedance 2 0 1 0 0 Clock input Open Output high 1 Crystal oscillation Crystal oscillation impedance 3 0 1 1 0 Clock input Open High 1 Crystal oscillation Crystal oscillation impedance 4 1 0 0 Open Open Clock input 5 1 0 1 Open Open Clock input 6 1 1 0 Open Open Clock input Notes Do not use in combination...

Page 138: ...stal resonator should be an AT cut parallel oscillator type Place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation High level Notes 1 The CKIO pin is an output in clock modes 0 1 and 2 In mode 3 it is high impedance 2 The v...

Page 139: ...in clock modes 0 1 2 and 3 CKPREQ CKM CKIO EXTAL XTAL Output or high impedance The CKIO pin is an output in clock modes 0 1 and 2 and is high impedance in clock mode 3 Open External Clock Input Ground level Figure 3 3 External Clock Input Method Clock Input from CKIO Pin This method can be used in clock modes 4 5 and 6 CKPREQ CKM CKIO EXTAL XTAL Open External Clock Input Open The CKPREQ CKM pin is...

Page 140: ...d not by an internal reset resulting from WDT overflow Its initial value depends on the settings of pins MD2 MD0 Table 3 4 shows the relationship between the MD2 MD0 pin combinations and the initial value of the frequency modification register Table 3 4 Relationship between Clock Mode Pin Settings and Initial Value of Frequency Modification Register Clock Mode MD2 MD1 MD0 Initial Value Mode 0 0 0 ...

Page 141: ... is not used Bit 5 CKIOST Setting is possible in modes 0 to 3 In modes 4 to 6 the CKIO pin is an input pin In these modes this bit always reads 1 Bit 5 CKIOST Description 0 The CKIO pin outputs Eφ 1 The CKIO pin is in the high impedance state Do not place CKIO in the high impedance state when PLL circuit 1 is operating Bit 4 Reserved This bit is always read as 0 The write value should always be 0 ...

Page 142: ... 4 2 2 1 Eφ 0 1 1 0 4 2 2 2 Eφ 1 0 0 0 4 4 1 1 Eφ 1 0 0 1 4 4 2 1 Eφ 1 0 1 0 4 4 2 2 Eφ 1 1 0 0 4 4 4 1 Eφ 1 1 1 0 4 4 4 2 Eφ Note Do not use combinations other than those shown above Modes 0 to 3 PLL circuit 1 halted PLL circuit 2 operating EXTAL input or crystal resonator used FR3 FR2 FR1 FR0 φ φ φ φ Iφ φ φ φ Eφ φ φ φ Pφ φ φ φ CKIO 0 0 0 0 1 1 1 1 Eφ 0 1 0 1 2 2 2 1 Eφ 0 1 1 0 2 2 2 2 Eφ 1 1 0 0...

Page 143: ...φ φ φ φ Iφ φ φ φ Eφ φ φ φ Pφ φ φ φ CKIO 0 0 0 0 4 1 1 1 Eφ 0 1 0 0 4 2 1 1 Eφ 1 0 0 0 4 4 1 1 Eφ Note Do not use combinations other than those shown above Modes 4 and 5 PLL circuit 1 operating PLL circuit 2 halted CKIO input FR3 FR2 FR1 FR0 φ φ φ φ Iφ φ φ φ Eφ φ φ φ Pφ φ φ φ CKIO 0 1 0 1 2 1 1 1 2 Eφ 0 1 1 0 2 1 1 1 Eφ 1 0 0 1 2 2 1 1 2 Eφ 1 0 1 0 2 2 1 1 Eφ Note Do not use combinations other than...

Page 144: ...e operating state access the frequency modification register using the following procedure and noting the cautions listed below Frequency change procedure Set the on chip watchdog timer WDT overflow time to secure the PLL circuit oscillation settling time CKS2 CKS0 bits in WTCSR Clear the WT IT and TME bit to 0 in WTCSR Perform a read anywhere in an external memory area 0 4 cache through area Chan...

Page 145: ...low SH7616 frequency change FMR equ h fffffe90 WTCSR equ h fffffe80 RSTCSR equ h fffffe83 PACR equ h fffffc80 XRAM equ h 1000e000 export _init_FMR _init_FMR mov l XRAM r1 mov l r1 r5 mov l FREQUENCY r2 mov l FREQUENCY_END r3 program_move mov w r2 r0 mov w r0 r1 add 2 r1 add 2 r2 cmp eq r2 r3 bf program_move nop mov l PACR r1 mov w h 0008 r0 mov w r0 r1 ...

Page 146: ...op nop nop Main portion of frequency change code First copy this to XRAM and then run it in XRAM FREQUENCY Watchdog timer control and status register setting Clear TME bit Clock input to WTCNT is φ 16384 Overflow frequency 262 144 ms MOV W R2 R1 External cache through area read Cache through area of external member space 3 H 26200000 MOV L R3 R0 Frequency change register setting PLL circuit 1 Disa...

Page 147: ... space 0 4 cache through area and the write to the frequency modification register should be performed in on chip X Y memory After reading from the external memory space 0 4 cache through area do not perform any write operations in external memory spaces 0 4 until the write to the frequency modification register When the write access to the frequency modification register is executed the WDT start...

Page 148: ... Input Frequency Range MHz PLL1 PLL2 Iφ φ φ φ MHZ Eφ φ φ φ MHZ Pφ φ φ φ MHZ CKIO Output MHz 0 1 EXTAL or crystal resonator 1 8 15 625 On On 8 62 5 8 62 5 8 31 25 8 62 5 Off On 8 62 5 8 62 5 8 31 25 8 62 5 On Off 8 62 5 8 15 625 8 15 625 8 15 625 1 31 25 Off Off 1 31 25 1 31 25 1 31 25 1 31 25 2 8 15 625 Off On 8 62 5 8 62 5 8 31 25 8 62 5 1 31 25 Off 1 31 25 1 31 25 1 31 25 1 31 25 3 8 15 625 On 8...

Page 149: ...ined after consultation with the crystal resonator manufacturer XTAL EXTAL R CL2 CL1 Avoid crossing signal lines Figure 3 5 Points for Attention when Using Crystal Resonator Bypass Capacitors As far as possible insert a laminated ceramic capacitor of 0 01 to 0 1 µF as a bypass capacitor for each VSS VCC pair Mount the bypass capacitors as close as possible to the LSI power supply pins and use comp...

Page 150: ...ot locate a wiring pattern in the vicinity CAP1 VCC PLL VCC C1 470 pF C2 470 pF VSS CAP2 VSS PLL Avoid crossing signal lines Power supply Reference values C1 C2 Figure 3 6 Points for Attention when Using PLL Oscillator Circuit 3 3 Bus Width of the CS0 Area Pins MD3 and MD4 are used to specify the bus width of the CS0 area The pin combination and functions are listed in table 3 6 Do not switch the ...

Page 151: ...g 4 1 Overview 4 1 1 Types of Exception Handling and Priority Order Exception handling is initiated by four sources resets address errors interrupts and instructions table 4 1 When several exception sources occur simultaneously they are accepted and processed according to the priority order shown in table 4 1 ...

Page 152: ...Compare match interrupt part of the bus state controller Ethernet controller EtherC and Ethernet controller direct memory access controller E DMAC 16 bit free running timer FRT Serial communication interface with FIFO SCIF 16 bit timer pulse unit TPU Serial I O with FIFO SIOF Serial I O SIO Instructions Trap instruction TRAPA General illegal instructions undefined code Illegal slot instructions un...

Page 153: ...tarts from the decoding of undefined code placed directly following a delayed branch instruction delay slot or of an instruction that rewrites the PC When exception handling starts the CPU operates as follows 1 Exception handling triggered by reset The initial values of the program counter PC and stack pointer SP are fetched from the exception vector table PC and SP are respectively addresses H 00...

Page 154: ...offsets Table 4 4 shows vector table address calculations Table 4 3 a Exception Vector Table Exception Source Vector Number Vector Table Address Offset Vector Address Power on reset PC 0 H 00000000 H 00000003 Vector number 4 SP 1 H 00000004 H 00000007 Manual reset PC 2 H 00000008 H 0000000B SP 3 H 0000000C H 0000000F General illegal instruction 4 H 00000010 H 00000013 VBR vector Reserved by system...

Page 155: ...ctor Table IRL Mode Exception Source Vector Number Vector Table Address Offset Vector Addresses Interrupt IRL1 1 64 2 H 00000100 H 00000103 VBR vector IRL2 1 65 2 H 00000104 H 00000107 number 4 IRL3 1 IRL4 1 66 2 H 00000108 H 0000010B IRL5 1 IRL6 1 67 2 H 0000010C H 0000010F IRL7 1 IRL8 1 68 2 H 00000110 H 00000113 IRL9 1 IRL10 1 69 2 H 00000114 H 00000117 IRL11 1 IRL12 1 70 2 H 00000118 H 0000011...

Page 156: ... The same vector number 10 is generated for a DMAC DMA address error and an E DMAC DMA address error See table 4 3 a Both the address error flag AE in the DMAC s DMA operation register DMAOR and the address error control bit AEC in the E DMAC s E DMAC operation control register EDOCR must therefore be read in the exception service routine to determine which DMA address error has occurred Table 4 4...

Page 157: ...n Reset When the NMI pin is high and the RES pin is driven low the device performs a power on reset For a reliable reset the RES pin should be kept low for at least the duration of the oscillation settling time when the PLL circuit is halted or for 20tpcyc when the PLL circuit is running During a power on reset the CPU s internal state and all on chip peripheral module registers are initialized Se...

Page 158: ...the frequency modification register FMR When the chip enters the manual reset state in the middle of a bus cycle manual reset exception handling does not start until the bus cycle has ended Thus manual resets do not abort bus cycles See appendix B Pin States for the state of individual pins in the manual reset state In a manual reset manual reset exception handling starts when the NMI pin is kept ...

Page 159: ...chronous DRAM mode setting space by PC relative addressing Address error occurs Access of cache purge space address array read write space data array read write space on chip peripheral module space or synchronous DRAM mode setting space by a TAS B instruction Address error occurs Byte word or longword data accessed in on chip peripheral module space at addresses H FFFFFC00 to H FFFFFCFF None norm...

Page 160: ...executed after the last instruction executed 3 The exception service routine start address is fetched from the exception vector table entry that corresponds to the address error that occurred and the program starts executing from that address The jump that occurs is not a delayed branch Note The same vector number 10 is generated for a DMAC DMA address error and an E DMAC DMA address error See tab...

Page 161: ...ce H UDI 1 IRL IRL1 IRL15 external input 15 IRQ IRQ0 IRQ3 external input 4 On chip peripheral module Direct memory access controller DMAC 2 Ethernet controller EtherC and Ethernet controller direct memory access controller E DMAC 1 16 bit free running timer FRT 3 Watchdog timer WDT 1 Bus state controller BSC 1 Serial I O with FIFO SIOF 4 Serial I O SIO 4 Serial communication interface with FIFO SC...

Page 162: ... Type Priority Level Comment NMI 16 Fixed priority level Cannot be masked User break 15 Fixed priority level H UDI 15 Fixed priority level IRL 1 15 Set with IRL3 IRL0 pins IRQ 0 15 Set with interrupt priority level setting register C IPRC On chip peripheral module 0 15 Set with interrupt priority level setting registers A B D and E IPRA IPRB IPRD IPRE 4 4 3 Interrupt Exception Handling When an int...

Page 163: ... BSR RTS RTE BF S BT S BSRF BRAF Instructions that rewrite the PC JMP JSR BRA BSR RTS RTE BT BF TRAPA BF S BT S BSRF BRAF General illegal instruction Undefined code anywhere besides in a delay slot 4 5 2 Trap Instructions When a TRAPA instruction is executed trap instruction exception handling starts The CPU operates as follows 1 The status register SR is saved to the stack 2 The program counter P...

Page 164: ... counter PC is saved to the stack The PC value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC 3 The exception service routine start address is fetched from the exception vector table entry that corresponds to the exception that occurred That address is jumped to and the program starts executing The jump that...

Page 165: ...ree instructions instruction fetch cycle not generated First instruction or last three instructions in a repeat loop containing four or more instructions Not accepted Not accepted Fourth from last instruction in a repeat loop containing four or more instructions Accepted Not accepted Notes 1 Delayed branch instructions JMP JSR BRA BSR RTS RTE BF S BT S BSRF BRAF 2 Interrupt disabled instructions L...

Page 166: ...cle of the fourth from last instruction For more information see the SH 1 SH 2 SH DSP Software Manual A All interrupts and address errors are accepted B Address errors only are accepted C No interrupts or address errors are accepted When RC 1 When RC 0 All interrupts and address errors are accepted 1 One instruction A B C A instr0 instr1 instr2 Start End 4 Four or more instructions A A or C on ret...

Page 167: ...e Stack Status Address error SP Address of instruction after executed instruction 32 bits SR 32 bits Trap instruction SP Address of instruction after TRAPA instruction 32 bits SR 32 bits General illegal instruction SP Start address of illegal instruction 32 bits SR 32 bits Interrupt SP Address of instruction after executed instruction 32 bits SR 32 bits Illegal slot instruction SP Jump destination...

Page 168: ...dress errors will continue to occur To ensure that address error exception handling does not go into an endless loop no address errors are accepted at that point This allows program control to be shifted to the address error exception service routine and enables error handling to be carried out When an address error occurs during exception handling stacking the stacking bus cycle write is executed...

Page 169: ...ers the priorities of on chip peripheral module interrupts can be selected at 16 levels for different request sources Vector numbers for on chip peripheral module interrupt can be set By setting the 24 vector number setting registers the vector numbers of on chip peripheral module interrupts can be set to values from 0 to 127 for different request sources The IRL interrupt vector number setting me...

Page 170: ...l Vector number Vector number DMAC Peripheral bus VCRWDT IPR UBC User break controller H UDI User debug interface DMAC Direct memory access controller FRT 16 bit free running timer WDT Watchdog timer REF Refresh request within bus state controller SCIF Serial communication interface with FIFO TPU 16 bit timer pulse unit SIO Serial I O SIOF Serial I O with FIFO E DMAC Ethernet controller direct mem...

Page 171: ...ting interrupt priority and controlling external interrupt input signal detection Table 5 2 Register Configuration Name Abbr R W Initial Value Address Access Size Interrupt priority register setting register A IPRA R W H 0000 H FFFFFEE2 8 16 Interrupt priority register setting register B IPRB R W H 0000 H FFFFFE60 8 16 Interrupt priority register setting register C IPRC R W H 0000 H FFFFFEE6 8 16 ...

Page 172: ...er T VCRT R W H 0000 H FFFFFECA 8 16 Vector number setting register U VCRU R W H 0000 H FFFFFECC 8 16 Vector number setting register WDT VCRWDT R W H 0000 H FFFFFEE4 8 16 Vector number setting register DMA0 4 VCRDMA0 R W Undefined H FFFFFFA0 32 Vector number setting register DMA1 4 VCRDMA1 R W Undefined H FFFFFFA8 32 Interrupt control register ICR R W H 8000 H 0000 1 H FFFFFEE0 8 16 IRQ control st...

Page 173: ...ister SR to level 15 See section 18 User Debug Interface for details of the H UDI interrupt 5 2 4 IRL Interrupts IRL interrupts are requested by input from pins IRL3 IRL0 Fifteen interrupts IRL15 IRL1 can be input externally via pins IRL3 IRL0 The priority levels of interrupts IRL15 IRL0 are 15 1 respectively and their vector numbers are 71 64 Set the vector numbers with the interrupt vector mode ...

Page 174: ...tor numbers External vector numbers are 0 to 127 and are input to the external vector input pins D7 D0 during the interrupt vector fetch bus cycle When an external vector is used 0 is input to D7 When an IRQ interrupt is accepted in external vector mode the IRQ interrupt priority level is output from the interrupt acceptance level output pins A3 A0 The external vector fetch signal IVECF is also as...

Page 175: ...Vector number generator circuit 4 IRL0 IRL3 IRL0 IRL3 D0 D7 A0 A3 IVECF RD D0 D7 Figure 5 2 Example of Connections for External Vector Mode Interrupts Chip Priority encoder Interrupt requests 4 IRL0 IRL3 IRL0 IRL3 Figure 5 3 Example of Connections for Auto Vector Mode Interrupts Figures 5 4 to 5 7 show the interrupt vector fetch cycle for the external vector mode During this cycle CS0 CS4 stay hig...

Page 176: ... CS4 BS A3 A0 IVECF RD WR RD D7 D0 T2 T3 T4 Vector number input High Accepted interrupt level Figure 5 4 External Vector Fetch Iφ φ φ φ Eφ φ φ φ 1 1 T1 CKIO CS0 CS4 BS A3 A0 IVECF RD WR RD D7 D0 T2 High Vector number input Accepted interrupt level Figure 5 5 External Vector Fetch Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 177: ...IT T1 T2 T3 Tw T4 Vector number input Accepted interrupt level High Figure 5 6 External Vector Fetch Iφ φ φ φ Eφ φ φ φ 1 1 WAIT WAIT WAIT WAIT Input CKIO CS0 CS4 BS A3 A0 IVECF RD WR RD D7 D0 WAIT T1 Tw T2 Accepted interrupt level High Vector number input Figure 5 7 External Vector Fetch Iφ φ φ φ Eφ φ φ φ 1 1 WAIT WAIT WAIT WAIT Input ...

Page 178: ...ule interrupt that was accepted 5 2 7 Interrupt Exception Vectors and Priority Order Table 5 4 lists interrupt sources and their vector numbers vector table address offsets and interrupt priorities Each interrupt source is allocated a different vector number and vector table address offset Vector table addresses are calculated from vector numbers and vector table address offsets In interrupt excep...

Page 179: ...within Interrupt Source Vector No Vector Table Address Order Initial Value IPR Bit Numbers IPR Setting Unit VCR Bit Numbers Default Priority NMI 11 VBR 16 High User break 12 vector No 15 H UDI 13 4 15 IRL15 4 71 1 15 IRL14 4 14 IRL13 4 70 1 13 IRL12 4 12 IRL11 4 69 1 11 IRL10 4 10 IRL9 4 68 1 9 IRL8 4 8 IRL7 4 67 1 7 IRL6 4 6 IRL5 4 66 1 5 IRL4 4 4 IRL3 4 65 1 3 IRL2 4 2 IRL1 4 64 1 1 DMAC0 Transf...

Page 180: ... 6 0 E DMAC EINT 6 0 127 2 15 0 0 IPRB High VCRA 14 8 15 12 Reserved VCRB 14 0 5 Low FRT ICI 0 127 2 15 0 0 IPRB High VCRC 14 8 OCI 0 127 2 11 8 VCRC 6 0 OVI 0 127 2 Low VCRD 14 8 TPU0 TGI0A 0 127 2 15 0 0 IPRD High VCRE 14 8 TGI0B 0 127 2 15 12 VCRE 6 0 TGI0C 0 127 2 VCRF 14 8 TGI0D 0 127 2 VCRF 6 0 TCI0V 0 127 2 Low VCRG 14 8 TPU1 TGI1A 0 127 2 15 0 0 IPRD High VCRH 14 8 TGI1B 0 127 2 11 8 VCRH ...

Page 181: ...27 2 Low VCRS 6 0 SIO2 RERI2 0 127 2 15 0 0 IPRE High VCRT 14 8 TERI2 0 127 2 3 0 VCRT 6 0 RDFI2 0 127 2 VCRU 14 8 TDEI2 0 127 2 Low VCRU 6 0 Reserved 128 255 Low Notes 1 An external vector number fetch can be performed without using the auto vector numbers shown in this table The external vector numbers are 0 127 2 Vector numbers are set in the on chip vector number register 3 REF is the refresh ...

Page 182: ...lue IPR Bit Numbers IPR Setting Unit VCR Bit Numbers Default Priority NMI 11 VBR 16 High User break 12 vector No 15 H UDI 13 4 15 IRQ0 4 64 1 15 0 0 IPRC 15 12 IRQ1 4 65 1 15 0 0 IPRC 11 8 IRQ2 4 66 1 15 0 0 IPRC 7 4 IRQ3 4 67 1 15 0 0 IPRC 3 0 DMAC0 Transfer end 0 127 2 15 0 0 IPRA 11 8 High Low VCRDMA0 6 0 DMAC1 Transfer end 0 127 2 15 0 0 High Low VCRDMA1 6 0 WDT ITI 0 127 2 15 0 0 IPRA 7 4 Hig...

Page 183: ...VCRD 14 8 TPU0 TGI0A 0 127 2 15 0 0 IPRD High VCRE 14 8 TGI0B 0 127 2 15 12 VCRE 6 0 TGI0C 0 127 2 VCRF 14 8 TGI0D 0 127 2 VCRF 6 0 TCI0V 0 127 2 Low VCRG 14 8 TPU1 TGI1A 0 127 2 15 0 0 IPRD High VCRH 14 8 TGI1B 0 127 2 11 8 VCRH 6 0 TCI1V 0 127 2 VCRI 14 8 TCI1U 0 127 2 Low VCRI 6 0 TPU2 TGI2A 0 127 2 15 0 0 IPRD High VCRJ 14 8 TGI2B 0 127 2 7 4 VCRJ 6 0 TCI2V 0 127 2 VCRK 14 8 TCI2U 0 127 2 Low ...

Page 184: ... 127 2 Low VCRU 6 0 Reserved 128 255 Low Notes 1 An external vector number fetch can be performed without using the auto vector numbers shown in this table The external vector numbers are 0 127 2 Vector numbers are set in the on chip vector number register 3 REF is the refresh control unit within the bus state controller 4 Set to IRL1 IRL15 or IRQ0 IRQ3 by the EXIMD bit in ICR 5 In the SH7616 VCRB...

Page 185: ...tial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R R R R Bits 15 to 12 Reserved These bits are always read as 0 The write value should always be 0 Bits 11 to 8 Direct Memory Access Controller DMAC Interrupt Priority Level 3 to 0 DMACIP3 DMACIP0 These bits set the direct memory access controller DMAC interrupt priority level There are four bits so levels 0 15 can be set The same level is set for both...

Page 186: ...lue 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bits 15 to 12 Ethernet Controller Direct Memory Access Controller E DMAC Interrupt Priority Level 3 to 0 E DMACIP3 E DMACIP0 These bits set the ethernet controller direct memory access controller E DMAC interrupt priority level There are four bits so levels 0 15 can be set ...

Page 187: ...not initialized in standby mode Bit 15 14 13 12 11 10 9 8 IRQ0IP3 IRQ0IP2 IRQ0IP1 IRQ0IP0 IRQ1IP3 IRQ1IP2 IRQ1IP1 IRQ1IP0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 IRQ2IP3 IRQ2IP2 IRQ2IP1 IRQ2IP0 IRQ3IP3 IRQ3IP2 IRQ3IP1 IRQ3IP0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 0 IRQ0 to IRQ3 Priority Level 3 to 0 IRQnIP3 IRQnIP...

Page 188: ... R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 TPU2IP3 TPU2IP2 TPU2IP1 TPU2IP0 SCF1IP3 SCF1IP2 SCF1IP1 SCF1IP0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 4 16 Bit Timer Pulse Unit 0 to 2 TPU0 TPU2 Interrupt Priority Level 3 to 0 TPUnIP3 TPUnIP0 n 0 2 These bits set the 16 bit timer pulse unit 0 to 2 TPU0 TPU2 interrupt priority levels There are four bits for each in...

Page 189: ... W R W R W R W Bits 15 to 12 Serial Communication Interface with FIFO 2 SCIF2 Interrupt Priority Level 3 to 0 SCF2IP3 SCF2IP0 These bits set the serial communication interface with FIFO 2 SCIF2 interrupt priority levels There are four bits so the value can be set between 0 and 15 Bits 11 to 8 Serial I O with FIFO SIOF Interrupt Priority Level 3 to 0 SIOFIP3 SIOFIP0 These bits set the serial I O wi...

Page 190: ...H 0 0000 to H F 1111 H 0 is interrupt priority level 0 the lowest H F is level 15 the highest When two on chip peripheral modules are assigned to the same bits DMAC0 and DMAC1 or WDT and BSC refresh control unit those two modules have the same priority A reset initializes IPRA IPRE to H 0000 They are not initialized in standby mode 5 3 6 Vector Number Setting Register WDT VCRWDT Vector number sett...

Page 191: ...tting Register A VCRA Vector number setting register A VCRA is a 16 bit read write register that sets the E DMAC interrupt vector numbers 0 127 VCRA is initialized to H 0000 by a reset It is not initialized in standby mode Bit 15 14 13 12 11 10 9 8 EINV6 EINV5 EINV4 EINV3 EINV2 EINV1 EINV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0...

Page 192: ... 16 bit free running timer FRT input capture interrupt and output compare interrupt vector numbers 0 127 VCRC is initialized to H 0000 by a reset It is not initialized in standby mode Bit 15 14 13 12 11 10 9 8 FICV6 FICV5 FICV4 FICV3 FICV2 FICV1 FICV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 FOCV6 FOCV5 FOCV4 FOCV3 FOCV2 FOCV1 FOCV0 Initial value 0 0 0 0 ...

Page 193: ...free running timer FRT overflow interrupt vector number 0 127 VCRD is initialized to H 0000 by a reset It is not initialized in standby mode Bit 15 14 13 12 11 10 9 8 FOVV6 FOVV5 FOVV4 FOVV3 FOVV2 FOVV1 FOVV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bits 15 and 7 to 0 Reserved These bits are always read as...

Page 194: ...TG0BV3 TG0BV2 TG0BV1 TG0BV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 0 TPU0 TGR0A Input Capture Compare Match Interrupt Vector Number 6 to 0 TG0AV6 TG0AV0 These bits set the vector number for the 16 bit timer pulse unit 0 TPU0 TGR0A input capture com...

Page 195: ...TG0DV3 TG0DV2 TG0DV1 TG0DV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 0 TPU0 TGR0C Input Capture Compare Match Interrupt Vector Number 6 to 0 TG0CV6 TG0CV0 These bits set the vector number for the 16 bit timer pulse unit 0 TPU0 TGR0C input capture com...

Page 196: ...ode Bit 15 14 13 12 11 10 9 8 TC0VV6 TC0VV5 TC0VV4 TC0VV3 TC0VV2 TC0VV1 TC0VV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bits 15 and 7 to 0 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 0 TPU0 TCNT0 Overflow Interrupt Vector Number 6 to 0 TC...

Page 197: ...TG1BV3 TG1BV2 TG1BV1 TG1BV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 1 TPU1 TGR1A Input Capture Compare Match Interrupt Vector Number 6 to 0 TG1AV6 TG1AV0 These bits set the vector number for the 16 bit timer pulse unit 1 TPU1 TGR1A input capture com...

Page 198: ... 2 1 0 TC1UV6 TC1UV5 TC1UV4 TC1UV3 TC1UV2 TC1UV1 TC1UV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 1 TPU1 TCNT1 Overflow Interrupt Vector Number 6 to 0 TC1VV6 TC1VV0 These bits set the vector number for the 16 bit timer pulse unit 1 TPU1 TCNT1 overflow...

Page 199: ...TG2BV3 TG2BV2 TG2BV1 TG2BV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 2 TPU2 TGR2A Input Capture Compare Match Interrupt Vector Number 6 to 0 TG2AV6 TG2AV0 These bits set the vector number for the 16 bit timer pulse unit 2 TPU2 TGR2A input capture com...

Page 200: ... 2 1 0 TC2UV6 TC2UV5 TC2UV4 TC2UV3 TC2UV2 TC2UV1 TC2UV0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 16 Bit Timer pulse unit 2 TPU2 TCNT2 Overflow Interrupt Vector Number 6 to 0 TC2VV6 TC2VV0 These bits set the vector number for the 16 bit timer pulse unit 2 TPU2 TCNT2 overflow...

Page 201: ...X1V4 SRX1V3 SRX1V2 SRX1V1 SRX1V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial Communication Interface with FIFO 1 SCIF1 Receive Error Interrupt Vector Number 6 to 0 SER1V6 SER1V0 These bits set the vector number for the serial communication interface with FIFO 1 SCIF1 re...

Page 202: ...TX1V5 STX1V4 STX1V3 STX1V2 STX1V1 STX1V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial Communication Interface with FIFO 1 SCIF1 Break Interrupt Vector Number 6 to 0 SBR1V6 SBR1V0 These bits set the vector number for the serial communication interface with FIFO 1 SCIF1 br...

Page 203: ...X2V4 SRX2V3 SRX2V2 SRX2V1 SRX2V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial Communication Interface with FIFO 2 SCIF2 Receive Error Interrupt Vector Number 6 to 0 SER2V6 SER2V0 These bits set the vector number for the serial communication interface with FIFO 2 SCIF2 re...

Page 204: ...TX2V5 STX2V4 STX2V3 STX2V2 STX2V1 STX2V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial Communication Interface with FIFO 2 SCIF2 Break Interrupt Vector Number 6 to 0 SBR2V6 SBR2V0 These bits set the vector number for the serial communication interface with FIFO 2 SCIF2 br...

Page 205: ... 7 6 5 4 3 2 1 0 TER0V6 TER0V5 TER0V4 TER0V3 TER0V2 TER0V1 TER0V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial I O with FIFO SIOF Receive Overrun Error Interrupt Vector Number 6 to 0 RER0V6 RER0V0 These bits set the vector number for the serial I O with FIFO SIOF receive...

Page 206: ... Bit 7 6 5 4 3 2 1 0 TDE0V6 TDE0V5 TDE0V4 TDE0V3 TDE0V2 TDE0V1 TDE0V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial I O with FIFO SIOF Receive Data Full Interrupt Vector Number 6 to 0 RDF0V6 RDF0V0 These bits set the vector number for the serial I O with FIFO SIOF receive...

Page 207: ... R W R W Bit 7 6 5 4 3 2 1 0 TER1V6 TER1V5 TER1V4 TER1V3 TER1V2 TER1V1 TER1V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial I O 1 SIO1 Receive Overrun Error Interrupt Vector Number 6 to 0 RER1V6 RER1V0 These bits set the vector number for the serial I O 1 SIO1 receive ove...

Page 208: ... R W R W R W Bit 7 6 5 4 3 2 1 0 TDE1V6 TDE1V5 TDE1V4 TDE1V3 TDE1V2 TDE1V1 TDE1V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial I O 1 SIO1 Receive Data Full Interrupt Vector Number 6 to 0 RDF1V6 RDF1V0 These bits set the vector number for the serial I O 1 SIO1 receive dat...

Page 209: ... R W R W Bit 7 6 5 4 3 2 1 0 TER2V6 TER2V5 TER2V4 TER2V3 TER2V2 TER2V1 TER2V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial I O 2 SIO2 Receive Overrun Error Interrupt Vector Number 6 to 0 RER2V6 RER2V0 These bits set the vector number for the serial I O 2 SIO2 receive ove...

Page 210: ...2 TDE2V1 TDE2V0 Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bits 15 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bits 14 to 8 Serial I O 2 SIO2 Receive Data Full Interrupt Vector Number 6 to 0 RDF2V6 RDF2V0 These bits set the vector number for the serial I O 2 SIO2 receive data full interrupt There are seven bits so the value can be set betw...

Page 211: ...0 Reserved Vector number setting register H Input capture compare match interrupt TPU1 TGR1A Input capture compare match interrupt TPU1 TGR1B Vector number setting register I Overflow interrupt TPU1 TCNT1 Underflow interrupt TPU1 TCNT1 Vector number setting register J Input capture compare match interrupt TPU2 TGR2A Input capture compare match interrupt TPU2 TGR2B Vector number setting register K ...

Page 212: ...orresponding 7 bit groups bits 14 to 8 and bits 6 to 0 with values in the range of H 00 0000000 to H 7F 1111111 H 00 is vector number 0 the lowest H 7F is vector number 127 the highest The vector table address is calculated by the following equation Vector table address VBR vector number 4 A reset initializes a vector number setting register to H 0000 They are not initialized in standby mode Table...

Page 213: ...ial value 0 1 0 0 0 0 0 0 0 R W R R R R R R R R W Bit 7 6 5 4 3 2 1 0 EXIMD VECMD Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R W R W Note When NMI input is high 1 when NMI input is low 0 Bit 15 NMI Input Level NMIL Sets the level of the signal input at the NMI pin This bit can be read to determine the NMI pin level This bit cannot be modified Bit 15 NMIL Description 0 NMI input level is low 1 N...

Page 214: ...tween 0 and 127 can be input as the vector number from the external vector number input pins D7 D0 Bit 0 VECMD Description 0 Auto vector mode vector number automatically set internally Initial value 1 External vector mode vector number set by external input 5 3 29 IRQ Control Status Register IRQCSR The IRQ control status register IRQCSR is a 16 bit register that sets the IRL0 IRL3 input signal det...

Page 215: ...cription 0 Low level is being input to pin IRLn 1 High level is being input to pin IRLn Note n 0 to 3 Bits 3 to 0 IRQ3 to IRQ0 Flags IRQ3F IRQ0F These bits indicate the IRQ3 IRQ0 interrupt request status Bit 3 0 IRQ3F IRQ0F Detection Setting Description 0 Level detection There is no IRQn interrupt request Initial value Clearing condition When IRLn input is high Edge detection An IRQn interrupt req...

Page 216: ...t with the interrupt mask bits I3 I0 in the CPU s status register SR If the request priority level is equal to or less than the level set in I3 I0 the request is held pending If the request priority level is higher than the level in bits I3 I0 the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU 4 The CPU detects the interrupt request sent from the interr...

Page 217: ... interrupt No Yes I3 to I0 level 0 No Program execution state Save SR to stack Save PC to stack Read vector number Branch to exception service routine Interrupt generated Copy accepted interrupt level to I3 I0 Read exception vector table I3 I0 Status register interrupt mask bits Note The vector number is only read from an external source when an external vector number is specified for the IRL IRQ ...

Page 218: ...ss 4n 8 4n 4 4n PC PC Start address of return destination instruction instruction after executing instruction SP 32 bits 32 bits SR Figure 5 9 Stack State after Interrupt Exception Handling 5 5 Interrupt Response Time Table 5 8 shows the interrupt response time which is the time from the occurrence of an interrupt request until interrupt exception handling starts and fetching of the first instruct...

Page 219: ...ndling SR and PC saves and vector address fetch until fetch of first instruction of exception service routine starts 5 0 Icyc m1 m2 m3 5 0 Icyc m1 m2 m3 5 0 Icyc m1 m2 m3 5 0 Icyc m1 m2 m3 Response time Total X 7 0 Icyc m1 m2 m3 X 5 5 Icyc 1 0 Ecyc 1 5 Pcyc m1 m2 m3 X 5 5 Icyc 1 0 Pcyc m1 m2 m3 X 5 0 Icyc 1 0 Pcyc m1 m2 m3 Minimum 10 11 9 5 9 Iφ Eφ Pφ 1 1 1 Maximum 11 2 m1 m2 m3 m4 19 5 2 m1 m2 m3...

Page 220: ...cording to the noise eliminated pin level so the pin level must be held until the CPU samples it This means that interrupt sources generally must not be cleared inside interrupt routines When an external vector is fetched the interrupt source can also be cleared when the external vector fetch cycle is detected Interrupt acceptance signal from CPU Interrupt request to CPU Noise canceler output Clea...

Page 221: ... the RTE instruction is used to return from interrupt handling as shown in figure 5 11 consider the cycles to be inserted between the read instruction for synchronization and the RTE instruction according to the set clock ratio Iφ Eφ Pφ and external bus cycle IRL3 IRL0 should be negated at least 0 5 Icyc 1 0 Ecyc 1 5 Pcyc before next interrupt acceptance becomes possible For example if clock ratio...

Page 222: ...r address operation is performed in accordance with result of decoding M Memory access Memory data access is performed W Write back Data read from memory is written to register Figure 5 11 Pipeline Operation when Returning by Means of RTE Instruction Interrupt clear instruction External write cycle External read cycle Write completed Next interrupt can be accepted Synchronization instruction IRL3 ...

Page 223: ...least 0 5 Icyc 1 0 Pcyc before next interrupt acceptance becomes possible For example if clock ratio Iφ Eφ Pφ is 4 2 2 at least 2 5 Icyc should be inserted b When changing level during interrupt handling When the SR value is changed by means of an LDC instruction and multiple implementation of other interrupts is enabled consider the cycles to be inserted between the synchronization instruction an...

Page 224: ...terrupt LDC instruction Interrupt disable instruction Normal instruction D E M M D E W D E D E D E 0 5Icyc 1 0Pcyc On chip peripheral read min 1 Icyc Figure 5 14 Pipeline Operation when Interrupts are Enabled by Means of SR Modification In the above figure the stage in which the instruction fetch occurs cannot be specified because of the mix of DSP instructions in this chip so instruction fetch F ...

Page 225: ...on independent or sequential conditions for channels A B C and D Sequential break settings Channel A channel B channel C channel D Channel B channel C channel D Channel C channel D 1 Address 32 bit masking capability individual address setting possible cache bus CPU internal bus DMAC E DMAC X Y bus 2 Data channels C and D only 32 bit masking capability individual address setting possible cache bus...

Page 226: ... address bus Internal interrupt signal Legend BARAH L Break address register AH L BAMRAH L Break address mask register AH L BBRA Break bus cycle register A BARBH L Break address register BH L BAMRBH L Break address mask register BH L BBRB Break bus cycle register B BARCH L Break address register CH L BAMRCH L Break address mask register CH L BDRCH L Break data register CH L BDMRCH L Break data mas...

Page 227: ... H 0000 H FFFFFF40 16 32 Break address register CL BARCL R W H 0000 H FFFFFF42 16 Break address mask register CH BAMRCH R W H 0000 H FFFFFF44 16 32 Break address mask register CL BAMRCL R W H 0000 H FFFFFF46 16 Break data register CH BDRCH R W H 0000 H FFFFFF50 16 32 Break data register CL BDRCL R W H 0000 H FFFFFF52 16 Break data mask register CH BDMRCH R W H 0000 H FFFFFF54 16 32 Break data mask...

Page 228: ...RL R W H 0000 H FFFFFF32 16 Branch flag register BRFR R 3 H FFFFFF10 16 32 Branch source register H BRSRH R Undefined H FFFFFF14 16 32 Branch source register L BRSRL R Undefined H FFFFFF16 16 Branch destination register H BRDRH R Undefined H FFFFFF18 16 32 Branch destination register L BRDRL R Undefined H FFFFFF1A 16 Notes 1 Initialized by a power on reset Value is retained in standby mode and is ...

Page 229: ...BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break address register A BARA consists of two 16 bit readable writable registers break address register AH BARAH and break address register AL BARAL BARAH specifies the upper half bits 31 to 16 of the address used as a channel A break condition and BARAL specifies the lower half bits 15 to 0 BARAH and B...

Page 230: ... R W Bit 7 6 5 4 3 2 1 0 BAMA7 BAMA6 BAMA5 BAMA4 BAMA3 BAMA2 BAMA1 BAMA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break address mask register A BAMRA consists of two 16 bit readable writable registers break address mask register AH BAMRAH and break address mask register AL BAMRAL BAMRAH specifies which bits of the break address set in BARAH are to be masked and BAMRAL spec...

Page 231: ...W R W R W R W R W R W R W R W Break bus cycle register A BBRA is a 16 bit readable writable register that sets four channel A break conditions 1 CPU cycle on chip DMAC DMAC E DMAC cycle 2 instruction fetch data access 3 read write and 4 operand size BBRA is initialized to H 0000 by a power on reset after a manual reset its value is undefined Bits 15 to 8 Reserved These bits are always read as 0 Th...

Page 232: ...r break interrupt is not generated Initial value 1 Read cycle is selected as break condition 1 0 Write cycle is selected as break condition 1 Read cycle or write cycle is selected as break condition Bits 1 and 0 Operand Size Select A SZA1 SZA0 These bits select the operand size of the bus cycle used as a channel A break condition Bit 1 SZA1 Bit 0 SZA0 Description 0 0 Operand size is not included i...

Page 233: ...3 BAB2 BAB1 BAB0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break address register B BARB consists of two 16 bit readable writable registers break address register BH BARBH and break address register BL BARBL BARBH specifies the upper half bits 31 to 16 of the address used as a channel B break condition and BARBL specifies the lower half bits 15 to 0 BARBH and BARBL are init...

Page 234: ... R W Bit 7 6 5 4 3 2 1 0 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break address mask register B BAMRB consists of two 16 bit readable writable registers break address mask register BH BAMRBH and break address mask register BL BAMRBL BAMRBH specifies which bits of the break address set in BARBH are to be masked and BAMRBL spec...

Page 235: ...W R W R W R W R W R W R W R W Break bus cycle register B BBRB is a 16 bit readable writable register that sets four channel B break conditions 1 CPU cycle on chip DMAC DMAC E DMAC cycle 2 instruction fetch data access 3 read write and 4 operand size BBRB is initialized to H 0000 by a power on reset after a manual reset its value is undefined Bits 15 to 8 Reserved These bits are always read as 0 Th...

Page 236: ...r break interrupt is not generated Initial value 1 Read cycle is selected as break condition 1 0 Write cycle is selected as break condition 1 Read cycle or write cycle is selected as break condition Bits 1 and 0 Operand Size Select B SZB1 SZB0 These bits select the operand size of the bus cycle used as a channel B break condition Bit 1 SZB1 Bit 0 SZB0 Description 0 0 Operand size is not included i...

Page 237: ...l value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break address register C BARC consists of two 16 bit readable writable registers break address register CH BARCH and break address register CL BARCL BARCH specifies the upper half bits 31 to 16 of the address used as a channel C break condition and BARCL specifies the lower half bits 15 to 0 The address bus connected to the X Y memory can...

Page 238: ...reak condition 6 2 8 Break Address Mask Register C BAMRC BAMRCH Bit 15 14 13 12 11 10 9 8 BAMC31 BAMC30 BAMC29 BAMC28 BAMC27 BAMC26 BAMC25 BAMC24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAMC23 BAMC22 BAMC21 BAMC20 BAMC19 BAMC18 BAMC17 BAMC16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W BAMRCL Bit 15 14 13 12 11 10 9 8 BAMC15 BAMC14...

Page 239: ...pecifies which bits of the break address set in BARCL are to be masked Operation also depends on bits XYEC and XYSC in BBRC as shown below BAMRC Configuration Upper 16 Bits BAMC31 to BAMC16 Lower 16 Bits BAMC15 to BAMC0 XYEC 0 Address Upper 16 bits maskable Lower 16 bits maskable XYEC 1 X address when XYSC 0 Maskable Y address when XYSC 1 Maskable Bit 31 to 0 BAMCn Description 0 Channel C break ad...

Page 240: ... R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDC7 BDC6 BDC5 BDC4 BDC3 BDC2 BDC1 BDC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break data register C BDRC consists of two 16 bit readable writable registers break data register CH BDRCH and break data register CL BDRCL BDRCH specifies the upper half bits 31 to 16 of the data used as a channel C break condition and BDRCL specifies ...

Page 241: ... W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMC23 BDMC22 BDMC21 BDMC20 BDMC19 BDMC18 BDMC17 BDMC16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W BDMRCL Bit 15 14 13 12 11 10 9 8 BDMC15 BDMC14 BDMC13 BDMC12 BDMC11 BDMC10 BDMC9 BDMC8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMC7 BDMC6 BDMC5 BDMC4 BDMC3 BDMC2 BDMC1 BDMC0 Initial value 0 0 0 0 ...

Page 242: ... Lower 16 bits maskable XYEC 1 X data when XYSC 0 Maskable Y data when XYSC 1 Maskable Bit 31 to 0 BDMCn Description 0 Channel C break data bit BDCn is included in break condition Initial value 1 Channel C break data bit BDCn is masked and not included in condition Notes 1 n 31 to 0 2 When including the data bus value in the break condition specify the operand size 3 When specifying byte size and ...

Page 243: ...d size BBRC is initialized to H 0000 by a power on reset after a manual reset its value is undefined Bits 15 to 10 Reserved These bits are always read as 0 The write value should always be 0 Bit 9 X Y Memory Bus Enable C XYEC Selects whether the X Y bus is used as a channel C break condition Bit 9 XYEC Description 0 Cache bus or internal bus is selected as condition for channel C address data Init...

Page 244: ... number of times a channel C break condition occurs before a user break interrupt is requested The maximum value is 212 1 times Each time a channel C break condition occurs the value in BETRC is decremented by 1 After the BETRC value reaches H 0001 an interrupt is requested when a break condition next occurs As exceptions and interrupts cannot be accepted for instructions in a repeat loop comprisi...

Page 245: ...0 Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Break address register D BARD consists of two 16 bit readable writable registers break address register DH BARDH and break address register DL BARDL BARDH specifies the upper half bits 31 to 16 of the address used as a channel D break condition and BARDL specifies the lower half bits 15 to 0 The address bus connected to the...

Page 246: ...reak condition 6 2 14 Break Address Mask Register D BAMRD BAMRDH Bit 15 14 13 12 11 10 9 8 BAMD31 BAMD30 BAMD29 BAMD28 BAMD27 BAMD26 BAMD25 BAMD24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BAMD23 BAMD22 BAMD21 BAMD20 BAMD19 BAMD18 BAMD17 BAMD16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W BAMRDL Bit 15 14 13 12 11 10 9 8 BAMD15 BAMD1...

Page 247: ...pecifies which bits of the break address set in BARDL are to be masked Operation also depends on bits XYED and XYSD in BBRD as shown below BAMRD Configuration Upper 16 Bits BAMD31 to BAMD16 Lower 16 Bits BAMD15 to BAMD0 XYED 0 Address Upper 16 bits maskable Lower 16 bits maskable XYED 1 X address when XYSD 0 Maskable Y address when XYSD 1 Maskable Bit 31 to 0 BAMDn Description 0 Channel D break ad...

Page 248: ...W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDD7 BDD6 BDD5 BDD4 BDD3 BDD2 BDD1 BDD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Break data register D BDRD consists of two 16 bit readable writable registers break data register DH BDRDH and break data register DL BDRDL BDRDH specifies the upper half bits 31 to 16 of the data used as a channel D break condition and BDRDL specifies...

Page 249: ...l value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMD23 BDMD22 BDMD21 BDMD20 BDMD19 BDMD18 BDMD17 BDMD16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W BDMRDL Bit 15 14 13 12 11 10 9 8 BDMD15 BDMD14 BDMD13 BDMD12 BDMD11 BDMD10 BDMD9 BDMD8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 BDMD7 BDMD6 BDMD5 BDMD4 B...

Page 250: ...5 to BDMD0 XYED 0 Data Upper 16 bits maskable Lower 16 bits maskable XYED 1 X data when XYSD 0 Maskable Y data when XYSD 1 Maskable Bit 31 to 0 BDMDn Description 0 Channel D break data bit BDDn is included in break condition Initial value 1 Channel D break data bit BDDn is masked and not included in condition Notes 1 n 31 to 0 2 When including the data bus value in the break condition specify the ...

Page 251: ...d size BBRD is initialized to H 0000 by a power on reset after a manual reset its value is undefined Bits 15 to 10 Reserved These bits are always read as 0 The write value should always be 0 Bit 9 X Y Memory Bus Enable D XYED Selects whether the X Y bus is used as a channel D break condition Bit 9 XYED Description 0 Cache bus or internal bus is selected as condition for channel D address data Init...

Page 252: ... number of times a channel D break condition occurs before a user break interrupt is requested The maximum value is 212 1 times Each time a channel D break condition occurs the value in BETRD is decremented by 1 After the BETRD value reaches H 0001 an interrupt is requested when a break condition next occurs As exceptions and interrupts cannot be accepted for instructions in a repeat loop comprisi...

Page 253: ...BED PCBD Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The break control register BRCR is used to make the following settings 1 Setting of independent channel mode or sequential condition mode for channels A B C and D 2 Selection of pre or post instruction execution break in case of an instruction fetch cycle 3 Selection of whether the data bus is to be included in the comparis...

Page 254: ... to be checked again after it has once been set the flag must be cleared by a write Bit 30 CMFPA Description 0 User break interrupt has not been generated by a channel A on chip DMAC cycle condition Initial value 1 User break interrupt has been generated by a channel A on chip DMAC cycle condition Bits 29 and 28 Reserved These bits are always read as 0 The write value should always be 0 Bit 27 PC ...

Page 255: ...ak conditions set for channel B is satisfied This flag is not cleared to 0 if the flag setting is to be checked again after it has once been set the flag must be cleared by a write Bit 22 CMFPB Description 0 User break interrupt has not been generated by a channel B on chip DMAC cycle condition Initial value 1 User break interrupt has been generated by a channel B on chip DMAC cycle condition Bit ...

Page 256: ...ted by a channel C CPU cycle condition Initial value 1 User break interrupt has been generated by a channel C CPU cycle condition Bit 14 DMAC Condition Match Flag C CMFPC This flag is set to 1 when an on chip DMAC bus cycle condition among the break conditions set for channel C is satisfied This flag is not cleared to 0 if the flag setting is to be checked again after it has once been set the flag...

Page 257: ...lways read as 0 The write value should always be 0 Bit 7 CPU Condition Match Flag D CMFCD This flag is set to 1 when a CPU bus cycle condition among the break conditions set for channel D is satisfied This flag is not cleared to 0 if the flag setting is to be checked again after it has once been set the flag must be cleared by a write Bit 7 CMFCD Description 0 User break interrupt has not been gen...

Page 258: ...ways read as 0 The write value should always be 0 Bit 3 Data Break Enable D DBED Selects whether a data bus condition is to be included in the channel D break conditions Bit 3 DBED Description 0 Data bus condition is not included in channel D conditions Initial value 1 Data bus condition is included in channel D conditions Bit 2 PC Break Select D PCBD Selects whether a channel D instruction fetch ...

Page 259: ... first out queue for PC trace use The queue is shifted at each branch Bits SVF and DVF are initialized by a power on reset but bits PID2 to PID0 are not Bit 15 Source Verify Flag SVF Indicates whether the address and pointer that enable the branch source address to be calculated have been stored in BRSR This flag is set when the instruction at the branch destination address is fetched and reset wh...

Page 260: ...ource Registers BRSR BRSRH Bit 31 30 29 28 27 26 25 24 BSA31 BSA30 BSA29 BSA28 BSA27 BSA26 BSA25 BSA24 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R R R R...

Page 261: ... R R R Bit 23 22 21 20 19 18 17 16 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R R R R R R R BRDRL Bit 15 14 13 12 11 10 9 8 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R W R R R R R R R R Bit 7 6 5 4...

Page 262: ... CPU condition match flag CMFCA CMFCB CMFCC CMFCD and DMAC condition match flag CMFPA CMFPB CMFPC CMFPD is also set for the matched condition for the respective channel 3 The INTC determines the priority of the user break interrupt As the priority level of a user break interrupt is 15 the interrupt is accepted if the level set in the interrupt mask bits I3 to I0 in the status register SR is 14 or ...

Page 263: ...or for the instruction following an instruction for which interrupts are prohibited such as LCD an interrupt is generated before execution of the next instruction at which interrupts are accepted 3 With the post execution condition an interrupt is generated after execution of the instruction set as the break condition and before execution of the following instruction As in 2 above a break cannot b...

Page 264: ... 31 to 1 of address bus Byte Bits 31 to 0 of break address register compared with bits 31 to 0 of address bus This means for example that if address H 00001003 is set without specifying a size condition bus cycles that satisfy the break conditions are as follows assuming that all other conditions are satisfied Longword access at address H 00001000 Word access at address H 00001002 Byte access at a...

Page 265: ...C value is the address at which the break occurs 3 When data access CPU on chip DMAC is set as break condition The value saved is the start address of the next instruction after the instruction for which execution has been completed when user break exception handling is initiated When data access CPU on chip DMAC is set as a break condition the point at which the break is to be made cannot be spec...

Page 266: ...en the break conditions for channels B and C are met at the same time the conditions for channel C are considered to be met If the break conditions for channels C and D are met at the same time and the conditions had not already been met for channel C the conditions are considered to be met for channel C Also if the conditions for channel C have already been met when the break conditions for chann...

Page 267: ...When a branch branch instruction repeat or interrupt occurs the address that enables the branch source address to be calculated and the branch destination address are stored in the branch source register BRSR and branch destination register BRDR The address stored in BRDR is the branch destination instruction fetch address The address stored in BRSR is the last instruction fetch address prior to t...

Page 268: ...er but the equations in the table do not take this into account Therefore the calculation can be performed using the values of BSA stored in BRSR and PID stored in BRFR 3 The location indicated by the address before branch occurrence IA differs according to the kind of branch a Branch instruction Branch instruction address b Repeat loop 2nd instruction from last in repeat loop Repeat_Start inst 1 ...

Page 269: ...independent Channel A Address H 00000404 address mask H 00000000 Bus cycle CPU instruction fetch post execution read operand size not included in conditions Channel B Address H 00003080 address mask H 0000007F Bus cycle CPU instruction fetch pre execution read operand size not included in conditions Channel C Address H 00008010 address mask H 00000006 Data H 00000000 data mask H 00000000 Bus cycle...

Page 270: ...el C Address H 00037226 address mask H 00000000 Data H 00000000 data mask H 00000000 Bus cycle CPU instruction fetch pre execution read word Channel D Address H 0003722E address mask H 00000000 Data H 00000000 data mask H 00000000 Bus cycle CPU instruction fetch pre execution read word On channel A a user break interrupt is not generated as an instruction fetch is not a write cycle On channel B a ...

Page 271: ...reak interrupt is not generated D Register settings BBRA H 0000 BARB H 00000500 BAMRB H 00000000 BBRB H 0057 BARC H 00000A00 BAMRC H 00000000 BBRC H 0057 BDRC H 00000000 BDMRC H 00000000 BARD H 00001000 BAMRD H 00000000 BBRD H 0057 BDRD H 00000000 BDMRD H 00000000 BRCR H 00102020 BETRC H 0005 BETRD H 000A Channel A Not used Channel B Address H 00000500 address mask H 00000000 Data H 00000000 data ...

Page 272: ...3456 address mask H 00000000 Bus cycle CPU data access read operand size not included in conditions Channel B Address H 01000000 address mask H 00000000 Bus cycle CPU data access read word Channel C Address H 000ABCDE address mask H 00000000 Data H 0000A512 data mask H 00000000 Bus cycle CPU data access write word Channel D Y address H 1001E000 address mask H FFFF0000 Data H 00004567 data mask H 0...

Page 273: ...cle On channel D a user break interrupt is generated when the DMAC writes H 7 Don t care is written by byte access to address H 00055555 6 3 9 Usage Notes 1 UBC registers can be read and written to only by the CPU 2 Note the following concerning sequential break specifications a As the CPU has a pipeline structure the order of instruction fetch cycles and memory cycles is determined by the pipelin...

Page 274: ...tion fetch post execution condition to perform step execution ensure that an address match does not occur during execution of the UBC s exception service routine 5 Note the following when specifying an instruction in a repeat loop that includes a repeat instruction as a break condition When an instruction in a repeat loop is specified as a break condition a A break will not occur during execution ...

Page 275: ...ion can be controlled for each space Control signals are output for each space Cache Cache area and cache through area can be selected by access address In cache access in the event of a cache access miss 16 bytes are read consecutively in 4 byte units to fill the cache Write through mode write back mode can be selected for writes In cache through access access is performed according to access siz...

Page 276: ... write mode or burst read burst write mode Bank active mode Bus arbitration All resources are shared with the CPU and use of the bus is granted on reception of a bus release request from off chip Refresh counter can be used as an interval timer Interrupt request generation on compare match CMI interrupt request signal ...

Page 277: ...WCR2 WCR3 Wait control unit WAIT CS4 CS0 BS STATS1 0 RD CAS RAS RD WR WE3 WE0 CKE REFOUT IVECF Interrupt controller Peripheral bus Module bus Internal bus Bus interface WCR Wait control register RTCSR Refresh timer control status register BCR Bus control register RTCNT Refresh timer counter MCR Individual memory control register RTCOR Refresh time constant register CMI interrupt request BCR1 BCR2 ...

Page 278: ...cle simultaneous with address output The start of the bus cycle can be determined by this signal CS0 CS4 O Hi Z Chip select CS3 is not asserted when the CS3 space is DRAM space RD WR O Hi Z Read write signal Signal that indicates access cycle direction read write Connected to WE pin when DRAM synchronous DRAM is connected RAS O Hi Z RAS pin for DRAM synchronous DRAM CAS OE O Hi Z Open when using D...

Page 279: ...M pin for the third byte D15 D8 For ordinary space indicates writing to the third byte DQMLL WE0 O Hi Z When synchronous DRAM is used connected to DQM pin for the least significant byte D7 D0 For ordinary space indicates writing to the least significant byte CAS3 O Hi Z When DRAM is used connected to CAS pin for the most significant byte D31 D24 CAS2 O Hi Z When DRAM is used connected to CAS pin f...

Page 280: ...pace other than CS0 until the settings for the interface to memory are completed Table 7 2 Register Configuration Name Abbr R W Initial Value Address 1 Access Size Bus control register 1 BCR1 R W H 03F0 H FFFFFFE0 16 2 32 Bus control register 2 BCR2 R W H 00FC H FFFFFFE4 16 2 32 Bus control register 3 BCR3 R W H 0F00 H FFFFFFFC 16 2 32 Wait control register 1 WCR1 R W H AAFF H FFFFFFE8 16 2 32 Wai...

Page 281: ...clude the associative purge space for cache purges address array read write space for reading and writing addresses address tags and data array read write space for forced reads and writes of data arrays Table 7 3 Address Map Address Space Memory Size H 00000000 H 01FFFFFF CS0 space cache area Ordinary space or burst ROM 32 Mbytes H 02000000 H 03FFFFFF CS1 space cache area Ordinary space 32 Mbytes...

Page 282: ...ved 1 H 60000000 H 7FFFFFFF Address array read write space 512 Mbytes H 80000000 H BFFFFFFF Reserved 1 H C0000000 H C0000FFF Data array read write space 4 kbytes H C0001000 H DFFFFFFF Reserved 1 H E0000000 H FFFEFFFF Reserved 1 H FFFF0000 H FFFF0FFF For setting synchronous DRAM mode 4 kbytes H FFFF1000 H FFFF7FFF Reserved 1 H FFFF8000 H FFFF8FFF For setting synchronous DRAM mode 4 kbytes H FFFFC00...

Page 283: ...erved This bit is always read as 0 The write value should always be 0 Bits 14 and 13 Long Wait Specification for Area 4 A4LW1 A4LW0 From 3 to 14 wait cycles are inserted in CS4 space accesses when the wait control bits W41 W40 in wait control register 2 WCR2 are set as long wait i e are set to 11 see table 7 4 Bit 12 Endian Specification for Area 2 A2ENDIAN In big endian format the MSB of byte dat...

Page 284: ...ts W11 W10 in wait control register 1 WCR1 are set as long wait i e are set to 11 see table 7 4 Bits 5 and 4 Long Wait Specification for Area 0 A0LW1 A0LW0 When the basic memory interface setting is made for CS0 from 3 to 14 wait cycles are inserted in CS0 accesses when the wait control bits W01 W00 in wait control register 1 WCR1 are set as long wait i e are set to 11 see table 7 4 Bit 3 Endian S...

Page 285: ...rved do not set 1 0 0 CS2 is synchronous DRAM space CS3 is ordinary space 1 CS2 and CS3 are synchronous DRAM spaces 1 0 Reserved do not set 1 Reserved do not set Table 7 4 Wait Values Corresponding to BCR1 and BCR3 Register Settings All Spaces BCR3 BCR1 AnLW2 AnLW1 AnLW0 Wait Value 0 0 0 3 cycles inserted 1 4 cycles inserted 1 0 5 cycles inserted 1 6 cycles inserted 1 0 0 8 cycles inserted 1 10 cy...

Page 286: ...er than CS0 until the register initialization ends The CS0 space bus size specification is set with pins MD4 and MD3 See section 3 3 CS0 Space Bus Width of the CS0 Area for details Bits 15 to 10 Reserved These bits are always read as 0 The write value should always be 0 Bits 9 and 8 Bus Size Specification for Area 4 CS4 A4SZ1 A4SZ0 Bit 9 A4SZ1 Bit 8 A4SZ0 Description 0 0 Longword 32 bit size Initi...

Page 287: ...ize Initial value Bits 1 and 0 Reserved These bits are always read as 0 The write value should always be 0 7 2 3 Bus Control Register 3 BCR3 Bit 15 14 13 12 11 10 9 8 A4LW2 AHLW2 A1LW2 A0LW2 Initial value 0 0 0 0 1 1 1 1 R W R R R R R W R W R W R W Bit 7 6 5 4 3 2 1 0 DSWW1 DSWW0 BASEL EDO BWE Initial value 0 0 0 0 0 0 0 0 R W R W R W R R R R W R W R W Initialize the BASEL EDO and BWE bits after a...

Page 288: ...it DSWW1 DSWW0 These bits determine the number of wait states inserted between DACK assertion and CASn assertion when writing to DRAM or EDO RAM in DMA single address mode Bit 7 DSWW1 Bit 6 DSWW0 Description 0 0 0 waits Initial value 1 1 wait 1 0 2 waits 1 Reserved do not set Bits 5 to 3 Reserved bits These bits are always read as 0 The write value should always be 0 Bit 2 Number of Banks Specific...

Page 289: ...er initialization are completed Bits 15 to 8 Idles between Cycles for Areas 3 to 0 IW31 IW00 These bits specify idle cycles inserted between consecutive accesses to different CS spaces Idles are used to prevent data conflict between ROM or the like which is slow to turn the read buffer off and fast memories and I O interfaces Even when access is to the same space idle cycles must be inserted when ...

Page 290: ...ntrol register 1 3 BCR1 BCR3 External wait input is enabled Initial value When CS3 is DRAM the number of CAS assert cycles is specified by wait control bits W31 and W30 Bit 7 W31 Bit 6 W30 Description 0 0 1 cycle 1 2 cycles 1 0 3 cycles 1 Reserved do not set When external wait mask bit A3WM in WCR2 is 0 and the number of CAS assert cycles is set to 2 or more external wait input is enabled When CS2...

Page 291: ...between acceptance of CS4 space external wait negation and RD or WEn negation Bit 15 A4WD1 Bit 14 A4WD0 Description 0 0 1 cycle Initial value 1 2 cycles 1 0 4 cycles 1 Reserved do not set Bit 13 Reserved bit This bit is always read as 0 The write value should always be 0 Bits 12 to 8 External Wait Mask Specification for Areas 0 to 4 A4WM A0WM These bits enable waits to be masked for CS spaces 0 to...

Page 292: ...n the same way as for CS 0 to 3 The set values below show the minimum number of idle cycles more cycles than indicated by the Idles between Cycles setting may actually be inserted Bit 3 IW41 Bit 2 IW40 Description 0 0 No idle cycle 1 One idle cycle inserted 1 0 Two idle cycles inserted Initial value 1 Four idle cycles inserted Bits 1 and 0 Wait Control for Area 4 W41 W40 These bits specify waits f...

Page 293: ...ts specify the number of cycles from address CS4 output to RD WEn assertion for the CS4 space Bit 13 A4SW2 Bit 12 A4SW1 Bit 11 A4SW0 Description 0 0 0 0 5 cycles Initial value 1 1 5 cycles 1 0 3 5 cycles 1 5 5 cycles 1 0 0 7 5 cycles 1 Reserved do not set 1 0 Reserved do not set 1 Reserved do not set Bit 10 Reserved bit This bit is always read as 0 The write value should always be 0 Bits 9 and 8 A...

Page 294: ...S0 BE RASD TRWL1 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 AMX2 SZ AMX1 AMX0 RFSH RMODE TRP1 RCD1 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The TRP1 TRP0 RCD1 RCD0 TRWL1 TRWL0 TRAS1 TRAS0 BE RASD AMX2 AMX0 and SZ bits are initialized after a power on reset Do not write to them thereafter When writing to them write the same values ...

Page 295: ...d or write command READ READA WRIT WRITA is issued Bit 0 RCD1 Bit 14 RCD0 Description 0 0 1 cycle Initial value 1 2 cycles 1 0 3 cycles 1 Reserved do not set Bits 8 and 13 Write Precharge Delay TRWL1 TRWL0 When the synchronous DRAM is not in the bank active mode this bit specifies the number of cycles after the write cycle before the start up of the auto precharge Based on this number of cycles th...

Page 296: ...re is a limit for the time from the issue of a refresh command until the next access This value is set to observe this limit Commands are not issued for TRAS cycles when self refresh is cleared Bit 12 TRAS1 Bit 11 TRAS0 Description 0 0 3 cycles Initial value 1 4 cycles 1 0 6 cycles 1 9 cycles Bit 10 Burst Enable BE Bit 10 BE Description 0 Burst disabled Initial value 1 High speed page mode during ...

Page 297: ...s left asserted When using this mode with an external device connected which performs writes other than to DRAM see section 7 6 5 Burst Access For synchronous DRAM access ends in the bank active state This is only valid for area 3 When area 2 is synchronous DRAM the mode is always auto precharge Bits 7 5 and 4 Address Multiplex AMX2 AMX0 For DRAM interface Bit 7 AMX2 Bit 5 AMX1 Bit 4 AMX0 Descript...

Page 298: ... 128 Mbit DRAM 8 M 16 bits 1 4 256 Mbit DRAM 8 M 32 bits 1 4 1 0 Reserved do not set 1 2 Mbit DRAM 128 k 16 bits Notes 1 Reserved Do not set when SZ bit in MCR is 0 16 bit bus width 2 See sction 7 5 11 for the method of connection to a 64 Mbit DRAM with a 2 M 32 bit configuration 3 See figure 7 2 for the method of connection to a 128 Mbit DRAM with a 4 M 32 bit configuration 4 In the case of a 128...

Page 299: ...00 A15 BA1 A14 BA0 A13 A11 A2 A0 CKIO CLK CKE CKE CSn CS RAS RAS CAS CAS RD WR WE D31 I O31 D0 I O0 DQMUU WE3 DQMUU DQMUL WE2 DQMUL DQMLU WE1 DQMLU DQMLL WE0 DQMLL 128 Mbit 1 Mword 32 bit 4 Bank synchronous DRAM Chip Figure 7 2 128 Mbit Synchronous DRAM 4 Mword 32 bit Connection Example ...

Page 300: ...11 A2 A0 CKIO CLK CKE CKE CSn CS RAS RAS CAS CAS RD WR D31 I O15 D16 I O0 DQMUU WE3 DQMU DQMUL WE2 DQML D15 D0 DQMLU WE1 BA1 DQMLL WE0 BA0 A11 A0 CLK CKE CS CAS WE I O15 I O0 DQMU DQML WE Chip 128 Mbit 2 Mword 16 bit 4 bank synchronous DRAM Figure 7 3 128 Mbit Synchronous DRAM 8 Mword 16 bit Connection Example ...

Page 301: ...and DRAM space the data bus width of BCR2 is ignored in favor of the specification of this bit Bit 6 SZ Description 0 Word 16 bits Initial value 1 Longword 32 bits Bit 3 Refresh Control RFSH This bit determines whether or not the refresh operation of DRAM synchronous DRAM is performed Bit 3 RFSH Description 0 No refresh Initial value 1 Refresh Bit 2 Refresh Mode RMODE When the RFSH bit is 1 this b...

Page 302: ...the interval timer are ignored during self refresh Bit 2 RMODE Description 0 Normal refresh Initial value 1 Self refresh 7 2 8 Refresh Timer Control Status Register RTCSR Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 CMF CMIE CKS2 CKS1 CKS0 RRC2 RRC1 RRC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 8 Reserved These ...

Page 303: ...S0 Bit 5 CKS2 Bit 4 CKS1 Bit 3 CKS0 Description 0 0 0 Count up disabled Initial value 1 Pφ 4 1 0 Pφ 16 1 Pφ 64 1 0 0 Pφ 256 1 Pφ 1024 1 0 Pφ 2048 1 Pφ 4096 Bits 2 to 0 Refresh Count RRC2 RRC0 These bits specify the number of consecutive refreshes to be performed when the refresh timer counter RTCNT and refresh time constant register RTCOR values match and a refresh request is issued Bit 2 RRC2 Bit...

Page 304: ...ts are always read as 0 The write value should always be 0 7 2 10 Refresh Time Constant Register RTCOR Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W RTCOR is an 8 bit read write register The values of RTCOR and RTCNT are constantly compared When the values correspond the compare matc...

Page 305: ...reading longword data from a byte width device requires four read operations The bus state controller automatically converts data alignment and data length between interfaces An 8 bit 16 bit or 32 bit external device data width can be connected by using the mode pins for the CS0 space or by setting BCR2 for the CS1 CS4 spaces However the data width of devices connected to the respective spaces is ...

Page 306: ...ddress 0 Byte read write of address 1 Byte read write of address 2 Byte read write of address 3 Word read write of address 0 Word read write of address 2 Longword read write of address 0 Figure 7 7 8 Bit External Devices and Their Access Units 7 3 2 Connection to Little Endian Devices The chip provides a conversion function in CS2 CS4 space for connection to and to maintain data compatibility with...

Page 307: ...device little endian D7 D0 15 8 7 0 7 0 7 0 A24 A0 000000 000001 000002 000003 000000 000002 000000 Data input output pin Byte read write of address 0 Byte read write of address 1 Byte read write of address 2 Byte read write of address 3 Word read write of address 0 Word read write of address 2 Longword read write of address 0 15 8 7 0 15 8 23 16 31 24 Figure 7 8 32 Bit External Devices and Their ...

Page 308: ...is asserted for 1 cycle to indicate the start of the bus cycle The CSn signal is negated by the fall of clock T2 to ensure the negate period The negate period is thus half a cycle when accessed at the minimum pitch The access size is not specified during a read The correct access start address will be output to the LSB of the address but since no access size is specified the read will always be 32...

Page 309: ...igure 7 11 Basic Timing of Ordinary Space Access When making a word or longword access with an 8 bit bus width or a longword access with a 16 bit bus width the bus state controller performs multiple accesses When clock ratio Iφ Eφ is other than 1 1 the basic timing shown in figure 7 11 is repeated but when clock ratio Iφ Eφ is 1 1 burst access with no CSn negate period is performed as shown in fig...

Page 310: ... T1 T2 Note DACKn waveform when active low is specified Figure 7 12 Timing of Longword Access in Ordinary Space Using 16 Bit Bus Width Clock Ratio Iφ φ φ φ Eφ φ φ φ 1 1 Figure 7 13 shows an example of 32 bit data width SRAM connection figure 7 14 an example of 16 bit data width SRAM connection and figure 7 15 an example of 8 bit data width SRAM connection ...

Page 311: ...9B0292 0200 A18 A2 CSn RD D31 D24 DQMUU WE3 D23 D16 DQMUL WE2 D15 D8 DQMLU WE1 D7 D0 DQMLL WE0 A16 A0 CS OE I O7 I O0 WE Chip 128 k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 7 13 Example of 32 Bit Data Width SRAM Connection ...

Page 312: ...RD D15 D8 DQMLU WE1 D7 D0 DQMLL WE0 A16 A0 CS OE I O7 I O0 WE Chip 128 k 8 bit SRAM A16 A0 CS OE I O7 I O0 WE Figure 7 14 Example of 16 Bit Data Width SRAM Connection A16 A0 CSn RD D7 D0 DQMLL WE0 A16 A0 CS OE I O7 I O0 WE Chip 128 k 8 bit SRAM Figure 7 15 Example of 8 Bit Data Width SRAM Connection ...

Page 313: ...specification bit AnLW in BCR1 BCR3 The long wait specification in BCR1 BCR3 can be made independently for CS0 CS1 and CS4 spaces but the same value must be specified for CS2 and CS3 spaces All WCR1 specifications are independent By means of WCR1 WCR2 BCR1 and BCR3 a Tw cycle is inserted as a wait cycle as long as the number of specified cycles at the wait timing for ordinary access space shown in...

Page 314: ... A4LW2 A4LW1 A4LW0 W41 W40 0 14 When a wait is specified by software using WCR1 and WCR2 Wn1 Wn0 and the external wait mask bit AnWM is cleared to 0 in WCR2 the wait input WAIT signal from outside is sampled Figure 7 17 shows WAIT signal sampling A 2 cycle wait is specified as a software wait The sampling is performed when the Tw state shifts to the T2 state so there is no effect even when the WAI...

Page 315: ...9B0292 0200 T1 Tw CKIO A24 A0 CSn RD WR RD D31 D0 WEn D31 D0 WAIT BS DACKn Read Write Tw Twx T2 Wait states from WAIT signal input Note DACKn waveform when active low is specified Figure 7 17 Wait State Timing of Ordinary Space Access Wait States from WAIT WAIT WAIT WAIT Signal ...

Page 316: ... space the number of cycles before CSn RD and WEn are negated after acceptance of external wait negation can be set as 1 2 or 4 by means of bits A4WD1 and A4WD0 in WCR2 Figure 7 18 shows an example T1 Tw CKIO A24 A0 CSn RD WR RD D15 D0 WEn D15 D0 WAIT BS DACKn Read Write Twx Twx T2 Specified by A4WD1 and A4WD0 in WCR2 A4WD1 A4WD0 01 Note DACKn waveform when active low is specified Figure 7 18 Wait...

Page 317: ...xible interfacing to external circuit The timing is shown in figure 7 19 Th and Tf cycles are added respectively before and after the ordinary cycle Signals other than RD and WEn are asserted in this cycle but RD and WEn are not In addition data is extended up to the Tf cycle which is effective for devices with slow write operations CKIO Address CSn BS RD Data WEn Data Th T1 T2 Tf DACKn RD WR Read...

Page 318: ...ported synchronous DRAM operating modes are burst read single write mode initial setting and burst read burst write mode The burst length depends on the data bus width comprising 8 bursts for a 16 bit width and 4 bursts for a 32 bit width The data bus width is specified by the SZ bit in MCR Burst operation is always performed so the burst enable BE bit in MCR is ignored Switching to burst write mo...

Page 319: ...s access For 16 bit data only DQMLU and DQMLL are used Figure 7 20 shows an example in which a 32 bit connection uses a 256 k 16 bit synchronous DRAM Figure 7 21 shows an example with a 16 bit connection A11 A2 CKIO CKE CSn RAS CAS OE RD WR D31 D16 DQMUU WE3 DQMUL WE2 D15 D0 DQMLU WE1 DQMLL WE0 A9 A0 CLK CKE CS RAS CAS WE I O15 I O0 DQMU DQML Chip 256 k 16 bit synchronous DRAM A9 A0 CLK CKE CS RAS...

Page 320: ...ionship between the multiplex specification bits and bit output to the address pins A24 A16 always output the original value regardless of multiplexing When SZ 0 the data width on the synchronous DRAM side is 16 bits and the LSB of the device s address pins A0 specifies word address The A0 pin of the synchronous DRAM is thus connected to the A1 pin of the SH7616 the rest of the connection proceedi...

Page 321: ...0 1 0 Column address A1 A8 A9 A10 A11 L H 1 A23 2 A14 A15 Row address A11 A18 A19 A20 A21 A22 A23 2 A24 A25 1 0 1 1 Column address A1 A8 A9 L H 1 A19 2 A12 A13 A14 A15 Row address A9 A16 A17 A18 A19 2 A20 A21 A22 A23 1 1 0 0 Column address A1 A8 A9 A10 A11 L H 1 A13 A22 3 A23 2 Row address A9 A16 A17 A18 A19 A20 A21 A22 3 A23 2 1 1 0 1 Column address A1 A8 A9 A10 A11 L H 1 A13 A23 3 A24 2 Row addr...

Page 322: ... 4 After a Tr cycle that performs ACTV command output a READA command is issued in the Tc cycle read data is accepted in cycles Td1 to Td4 and the end of the read sequence is waited for in the Tde cycle One Tde cycle is issued when Iφ Eφ 1 1 and two cycles when Iφ Eφ 1 1 Tap is a cycle for waiting for the completion of the auto precharge based on the READA command within the synchronous DRAM Durin...

Page 323: ... When the CAS latency is 2 or more a Tap cycle equal to the TRP specification 1 is generated During the Tap cycle no commands other than NOP are issued to the same bank Figure 7 23 a and b show examples of burst read timing when RCD1 RCD0 is 01 W31 W30 is 01 and TRP1 TRP0 is 01 When the data width is 16 bits 8 burst cycles are required for a 16 byte data transfer The data fetch cycle goes from Td1...

Page 324: ... page 298 of 906 REJ09B0292 0200 Tr Tc CKIO A24 A11 A10 A9 A1 CS2 or CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Td1 Td2 Td3 Td4 Tde Tde Tap Note DACKn waveform when active low is specified Figure 7 22 b Basic Burst Read Timing Auto Precharge Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 325: ...06 REJ09B0292 0200 Tr CKIO A24 A11 A10 A9 A1 CS2 or CS3 RAS CAS RD WR DQMxx D31 D0 DACKn TrW Tc Tw Td1 Td2 Td3 Td4 Tde Tap Note DACKn waveform when active low is specified Figure 7 23 a Burst Read Wait Specification Timing Auto Precharge Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 326: ...of 906 REJ09B0292 0200 Tr CKIO A24 A11 A10 A9 A1 CS2 or CS3 RAS CAS RD WR DQMxx D31 D0 DACKn TrW Tc Tw Td1 Td2 Td3 Td4 Tde Tde Tap Note DACKn waveform when active low is specified Figure 7 23 b Burst Read Wait Specification Timing Auto Precharge Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 327: ...burst read mode the read data output continues after the required data is received To avoid data conflict an empty read cycle is performed from Td2 to Td4 after the required data is read in Td1 and the device waits for the end of synchronous DRAM operation When the data width is 16 bits the number of burst transfers during a read is 8 Data is fetched in cache through and other DMA read cycles only...

Page 328: ...page 302 of 906 REJ09B0292 0200 Tr Tc CKIO A24 A11 A10 A9 A1 CS2 or CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Td1 Td2 Td3 Td4 Tde Tap Note DACKn waveform when active low is specified Figure 7 24 a Single Read Timing Auto Precharge Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 329: ...rite accesses After the ACTV command Tr a WRITA command is issued in Tc to perform an auto precharge In the write cycle the write data is output simultaneously with the write command When writing with an auto precharge the bank is precharged after the completion of the write command within the synchronous DRAM so no command can be issued to that bank until the precharge is completed For that reaso...

Page 330: ...n in figure 7 26 a and b This example assumes a 32 bit bus width and a burst length of 4 In the burst write cycle the WRITA command that performs auto precharge is issued in Tc1 following the ACTV command Tr cycle The first 4 bytes of write data are output simultaneously with the WRITA command in Tc1 and the remaining 12 bytes of data are output consecutively in Tc2 Tc3 and Tc4 In a write with aut...

Page 331: ...x signal high These empty cycles increase the memory access time and tend to reduce program execution speed and DMA transfer speed Therefore unnecessary cache through area accesses should be avoided and copy back should be selected for the cache setting Also in DMA transfer it is important to use a data structure that allows transfer in 16 bit units Tr Tc1 CKIO A24 A11 A10 A9 A1 CS2 or CS3 RAS CAS...

Page 332: ...T In this case even when the access is completed no precharge is performed This function is not supported in the CS2 space When the bank active function is used no precharge is performed when the access is completed When accessing the same row address in the same bank a READ or WRIT command can be called immediately without calling an ACTV command just like the RAS down mode of the DRAM s high spe...

Page 333: ...fresh and the refresh cycle must be set to the maximum value tRAS or less This enables the limit on the maximum active period for each bank to be ensured When auto refresh is not being used some measure must be taken in the program to ensure that the bank does not stay active for longer than the prescribed period Figure 7 27 a and b show burst read cycles that is not an auto precharge cycle figure...

Page 334: ...ome inactive even in the bank active mode after the refresh cycle ends or after the bus is released by bus arbitration Tr Tc CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Td1 Td2 Td3 Td4 Tde Note DACKn waveform when active low is specified Figure 7 27 a Burst Read Timing No Precharge Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 335: ...r 09 2006 page 309 of 906 REJ09B0292 0200 Tr Tc CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Td1 Td2 Td3 Td4 Tde Tde Note DACKn waveform when active low is specified Figure 7 27 b Burst Read Timing No Precharge Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 336: ...ge 310 of 906 REJ09B0292 0200 Tnop CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Tc Td1 Td2 Td3 Td4 Tde Note DACKn waveform when active low is specified Figure 7 28 a Burst Read Timing Bank Active Same Row Address Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 337: ... page 311 of 906 REJ09B0292 0200 Tc Tnop CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Td1 Td2 Td3 Td4 Tde Tde Note DACKn waveform when active low is specified Figure 7 28 b Burst Read Timing Bank Active Same Row Address Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 338: ...12 of 906 REJ09B0292 0200 Tp Tr CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Tc Td1 Td2 Td3 Td4 Tde Note DACKn waveform when active low is specified Figure 7 29 a Burst Read Timing Bank Active Different Row Addresses Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 339: ...e 313 of 906 REJ09B0292 0200 Tp Tr CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Tc Td1 Td2 Td3 Td4 Tde Tde Note DACKn waveform when active low is specified Figure 7 29 b Burst Read Timing Bank Active Different Row Addresses Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 340: ...oller BSC Rev 2 00 Mar 09 2006 page 314 of 906 REJ09B0292 0200 CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Tr Tc Note DACKn waveform when active low is specified Figure 7 30 Single Write Mode Timing No Precharge ...

Page 341: ...SC Rev 2 00 Mar 09 2006 page 315 of 906 REJ09B0292 0200 CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Tc Note DACKn waveform when active low is specified Figure 7 31 Single Write Mode Timing Bank Active Same Row Address ...

Page 342: ... 2 00 Mar 09 2006 page 316 of 906 REJ09B0292 0200 CKIO A24 A11 A10 A9 A1 CS3 RAS CAS RD WR DQMxx D31 D0 DACKn Tp Tr Tc Note DACKn waveform when active low is specified Figure 7 32 Single Write Mode Timing Bank Active Different Row Addresses ...

Page 343: ...TCNT starts counting up from the value at that time The RTCNT value is constantly compared to the RTCOR value and when the two values match a refresh request is made and the number of auto refreshes set in RRC2 RRC0 are performed RTCNT is cleared to 0 at that time and the count up starts again Figure 7 33 shows the timing for the auto refresh cycle First a PALL command is issued during the Tp cycl...

Page 344: ...learing and data retention are performed correctly and auto refreshing is performed without delay at the correct intervals When self refresh mode is entered while the synchronous DRAM is set for auto refresh or when leaving the standby mode with a manual reset or NMI auto refresh can be re started if RFSH is 1 and RMODE is 0 when the self refresh mode is cleared When time is required between clear...

Page 345: ...T pin is provided to send a signal requesting the bus right during the wait for refreshing to be executed REFOUT is asserted until the bus is acquired If RTCNT and RTCOR match and a new refresh request occurs while waiting for the refresh to execute the previous refresh request is erased To make sure the refresh executes properly be sure that the bus cycle and bus capture do not exceed the refresh...

Page 346: ...he number of Tap cycles than it actually does Specific cases in which an overlap occurs are listed in table 7 7 Also figure 7 35 shows is a conceptual diagram of an overlap that occurs when memory spaces CS2 and CS3 are connected to SDRAM table 7 7 No 3 Table 7 7 Cases of Overlap Between Tap Cycle and Next Access No First Access Second Access 1 Space CS3 auto precharge Access to different space am...

Page 347: ... at this time but the mode is written using word as the size Write any data in word size to the following addresses to select the burst read single write supported by the chip a CAS latency of 1 to 3 a sequential wrap type and a burst length of 8 or 4 depending on whether the width is 16 bits or 32 bits Burst Read Single Write For 16 bits CAS latency 1 CAS latency 2 CAS latency 3 H FFFF0426 H FFFF...

Page 348: ...ardless of the MCR setting After writing to the synchronous DRAM mode register perform a dummy read to each synchronous DRAM bank before starting normal access This will initialize the SH7616 s internal address comparator Synchronous DRAM requires a fixed idle time after powering on before the all bank precharge command is issued Refer to the synchronous DRAM manual for the necessary idle time Whe...

Page 349: ...Mword 32 bit SDRAM A12 A11 A10 A0 CLK CKE CS RAS CAS WE I O31 I O0 DQMUU DQMUL DQMLU DQMLL Figure 7 37 64 Mbit Synchronous DRAM 2 Mword 32 bit Connection Example Bus Status Controller BSC Register Settings Set the individual bits in the memory control register MCR as follows MCR bit 6 SZ 1 MCR bit 7 AMX2 0 MCR bit 5 AMX1 0 MCR bit 4 AMX0 0 Synchronous DRAM Mode Settings To make mode settings for t...

Page 350: ...be 16 or 32 bits figures 7 38 and 7 39 Two CAS 16 bit DRAMs can be connected since CAS is used to control byte access The RAS CAS3 CAS0 and RD WR signals are used to connect the DRAM When the data width is 16 bits CAS3 and CAS2 are not used In addition to ordinary read and write access burst access using high speed page mode is also supported A10 A2 D15 D0 RAS RD WR D31 D16 CAS3 CAS2 A8 A0 RAS OE ...

Page 351: ... There are four ways of multiplexing which can be selected using the AMX1 AMX0 bits in MCR Table 7 8 illustrates the relationship between the AMX1 AMX0 bits and address multiplexing Address multiplexing is performed on address output pins A15 A1 The original addresses are output to pins A24 A16 During DRAM accesses AMX2 is reserved so set it to 0 Table 7 8 Relationship between AMX1 AMX0 and Addres...

Page 352: ... is the RAS assert cycle Tc1 is the CAS assert cycle and Tc2 is the read data fetch cycle When accesses are consecutive the Tp cycle of the next access overlaps the Tc2 cycle of the previous access so accesses can be performed in a minimum of 3 cycles each Tp Tr CKIO A24 A16 A15 A1 RAS CASn RD WR RD D31 D0 RD WR RD D31 D0 DACKn Read Write Tc1 Tc2 Note DACKn waveform when active low is specified Fi...

Page 353: ...cle to 3 cycles by inserting a Trw cycle by means of the RCD1 RCD0 bit in MCR The number of cycles from CASn assert to the end of access can be extended from 1 cycle to 3 cycles by setting the W31 W30 bits in WCR1 When external wait mask bit A3WM in WCR2 is cleared to 0 and bits W31 and W30 in WCR1 are set to a value other than 00 the external wait pin is also sampled so the number of cycles can b...

Page 354: ... Rev 2 00 Mar 09 2006 page 328 of 906 REJ09B0292 0200 Tp Tpw CKIO A24 A16 A15 A1 RAS CASn RD WR RD D31 D0 RD WR RD D31 D0 DACKn Read Write Note DACKn waveform when active low is specified Tr Trw Tc1 Tw Tc2 Figure 7 41 Wait State Timing ...

Page 355: ...ecified Figure 7 42 External Wait State Timing 7 6 5 Burst Access In addition to the ordinary mode of DRAM access in which row addresses are output at every access and data is then accessed DRAM also has a high speed page mode for use when continuously accessing the same row that enables fast access of data by changing only the column address after the row address is output Select ordinary access ...

Page 356: ...is used and the BE bit in MCR is set to 1 setting the MCR s RASD bit which specifies RAS down mode to 1 places the SH7616 in RAS down mode which leaves the RAS signal asserted The access timing in RAS down mode is shown in figures 7 44 and 7 45 When RAS down mode is used the refresh cycle must be less than the maximum DRAM RAS assert time tRAS when the refresh cycle is longer than the tRAS maximum...

Page 357: ...00 Mar 09 2006 page 331 of 906 REJ09B0292 0200 CKIO A24 A14 A13 A1 RAS CASn RD WR RD D31 D0 RD WR RD D31 D0 DACKn Read Write Tc1 Tc2 Note DACKn waveform when active low is specified Figure 7 44 RAS RAS RAS RAS Down Mode Same Row Access Timing ...

Page 358: ...e 7 45 RAS RAS RAS RAS Down Mode Different Row Access Timing 7 6 6 EDO Mode In addition to the kind of DRAM in which data is output to the data bus only while the CASn signal is asserted in a data read cycle there is another kind provided with an EDO mode in which while both RAS and OE are asserted once the CASn signal is asserted data is output to the data bus until CASn is next asserted even tho...

Page 359: ...the DRAM Ordinary access in EDO mode is shown in figure 7 48 and burst access in figure 7 49 In EDO mode in order to extend the timing for data output to the data bus in a read cycle until the next assertion of CASn the DRAM access time can be increased by delaying the data latch timing by 1 2 cycle making it at the rise of the CKIO clock A8 A0 RAS OE WE I O15 I O0 UCAS LCAS A8 A0 RAS OE WE I O15 ...

Page 360: ...troller BSC Rev 2 00 Mar 09 2006 page 334 of 906 REJ09B0292 0200 A8 A0 RAS OE WE I O15 I O0 UCAS LCAS A9 A1 RAS RD WR D15 D0 CAS1 CAS0 CAS OE 256 k 16 bit DRAM Chip Figure 7 47 Example of EDO DRAM Connection 16 Bit Data Width ...

Page 361: ... of 906 REJ09B0292 0200 Tr Tc1 CKIO A24 A16 A15 A1 RD WR RAS CASn D15 D0 CAS OE D15 D0 CAS OE DACKn Read Note DACKn waveform when active low is specified Write Tc2 Tpc Row address Column address Row address High level Figure 7 48 DRAM EDO Mode Ordinary Access Timing ...

Page 362: ...dress High Figure 7 49 DRAM EDO Mode Burst Access Timing 7 6 7 DRAM Single Transfer Wait states equivalent to the value set in bits DSWW1 and DSWW0 in BCR3 can be inserted between DACKn assertion and CASn assertion in a write in DMA single address transfer mode Inserting wait states allows the data setup time for external device memory Figure 7 50 shows the write cycle timing in DMA single transfe...

Page 363: ...e RAS refresh cycle can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR Consecutive refreshes can be generated by setting bits RRC2 RRC0 in RTCSR If DRAM is not accessed for a long period self refresh mode which uses little power consumption for data retention can be activated by setting both the RMODE and RFSH bits to 1 CAS CAS CAS CAS Before RAS RAS RAS RAS Refre...

Page 364: ... of bits TRP1 and TRP0 in MCR Tp Trr CKIO RAS CASn RD WR RD Trc1 Trc2 Tre Figure 7 51 DRAM CAS CAS CAS CAS before RAS RAS RAS RAS Refresh Cycle Timing Self Refreshing A self refresh is started by setting both the RMODE bit and the RFSH bit to 1 During the self refresh DRAM cannot be accessed Self refreshing is cleared by clearing the RMODE bit to 0 Self refresh timing is shown in figure 7 52 Setti...

Page 365: ... sequence must be implemented by the initialization program executed after a power on reset 7 7 Burst ROM Interface Set the BSTROM bit in BCR1 to set the CS0 space for connection to burst ROM The burst ROM interface is used to permit fast access to ROMs that have the nibble access function Figure 7 54 shows the timing of nibble accesses to burst ROM Set for two wait cycles The access is basically ...

Page 366: ...ROM access the WAIT pin is sampled When the burst ROM is set and 0 specified for waits there are 2 access cycles from the second time on Figure 7 55 shows the timing T1 Tw T2 Tw T2 Tw T2 Tw T2 8 bit bus width longword access T1 Tw T2 Tw T2 8 bit bus width word access T1 Tw T2 8 bit bus width byte access T1 Tw T2 Tw T2 16 bit bus width longword access T1 Tw T2 16 bit bus width word access T1 Tw T2 ...

Page 367: ...oller BSC Rev 2 00 Mar 09 2006 page 341 of 906 REJ09B0292 0200 T1 Tw1 CKIO A24 A0 CS0 RD WR RD D31 D0 BS DACKn Tw2 T2 Tw1 Tw2 T2 Note DACKn waveform when active low is specified Figure 7 54 Burst ROM Nibble Access 2 Wait States ...

Page 368: ... Controller BSC Rev 2 00 Mar 09 2006 page 342 of 906 REJ09B0292 0200 T1 T2 CKIO A24 A0 CS0 RD WR RD D31 D0 BS DACKn T1 T2 Note DACKn waveform when active low is specified Figure 7 55 Burst ROM Nibble Access No Wait States ...

Page 369: ...S space since data is output from the same data buffer The number of idle cycles to be inserted into the access cycle when reading from another CS space or performing a write after a read from the CS3 space is specified by the IW31 and IW30 bits in WCR1 Likewise IW21 and IW20 specify the number of idle cycles after CS2 reads IW11 and IW10 specify the number after CS1 reads and IW01 and IW00 specif...

Page 370: ...00 T1 T2 CKIO A24 A0 CSm CSn BS RD WR RD D31 D0 Twait T1 T2 Twait T1 T2 CSm space read CSn space read CSn space write Specification of waits between CSm accesses reading different spaces Specification of waits between CSn accesses read followed by write Figure 7 56 Idles between Cycles ...

Page 371: ... mode or round robin mode can be selected by means of the priority mode bit PR in the DMA operation register DMAOR When the bus is being passed between slave and master all bus control signals are negated before the bus is released to prevent erroneous operation of the connected devices When the bus is transferred also the bus control signals begin bus driving from the negated state The master and...

Page 372: ...t connects the CPU DMAC and on chip peripheral modules can operate in parallel to the external bus both read and write accesses from the CPU to on chip peripheral modules and from the DMAC to on chip peripheral modules are possible even if the external bus is not held Figures 7 57 a and 7 57 b show the timing charts in the cases that bus requests occur simultaneously from the E DMAC DMAC and CPU T...

Page 373: ... Controller BSC Rev 2 00 Mar 09 2006 page 347 of 906 REJ09B0292 0200 CPU DMAC E DMAC CPU CKIO A24 A0 CS0 RD CS2 CS3 RAS CAS RD WR D31 D0 Figure 7 57 a Bus Arbitration Timing E DMAC Read DMAC 16 Byte Transmission CPU Read ...

Page 374: ... Controller BSC Rev 2 00 Mar 09 2006 page 348 of 906 REJ09B0292 0200 CPU DMAC E DMAC CPU CKIO A24 A0 CS0 RD CS2 CS3 RAS CAS RD WR D31 D0 Figure 7 57 b Bus Arbitration Timing E DMAC Write DMAC 16 Byte Transmission CPU Read ...

Page 375: ...l signals BS CSn RAS CASn WEn RD RD WR become high impedance at a rise of the clock These bus control signals are driven high at least 2 cycles before they become high impedance Sampling for bus request signals occurs at the clock fall The sequence when the bus is taken back from the slave is as follows When the negation of BRLS is detected at a clock fall high level driving of the bus control sig...

Page 376: ...bus master ends the access in a longword unit since the access request is canceled by the manual reset This means that when a manual reset is executed during a cache filling the cache contents can no longer be guaranteed During a manual reset the RTCNT does not count up so no refresh request is generated and a refresh cycle is not initiated To preserve the data of the DRAM and synchronous DRAM the...

Page 377: ...gword reads occur For misses that occur when byte or word operands are accessed or branches occur to odd word boundaries 4n 2 addresses the filling is always performed by longword accesses on the chip external interface In the cache through area the access is to the actual access address When the access is an instruction fetch the access size is always longword For cache through areas and on chip ...

Page 378: ...he write cycle When both the source address and destination address of the DMA are external spaces to the chip however it must wait until the completion of the previous write cycle before starting the next read cycle The E DMAC can perform access involving external memory but not access involving any on chip memory or peripheral modules 7 10 3 STATS1 and STATS0 Pins The SH7616 has two pins STATS1 ...

Page 379: ...s in the high impedance state while keeping the SH7616 s internal state halted The conditions for establishing the high impedance state the applicable pins and the bus timing figure 7 60 are shown below See the Application Note for an example of PCI bridge connection High impedance conditions Not dependent on BCR settings etc when WAIT L and BUSHiZ L Applicable pins A 24 0 D 31 0 CS3 RD WR RD RAS ...

Page 380: ...IO figure 7 61 As there is a risk of an erroneous write to normal space in this case when synchronous DRAM or a high speed device is connected to normal space it is recommended that CSn be delayed on the system side Cases in which a synchronous DRAM write and normal space access occur consecutively are shown in table 7 10 Table 7 10 access sequence Write to Synchronous DRAM Normal Space Access CPU...

Page 381: ...T1 CKIO CS2 or CS3 RAS CAS RD WR DQM WEn CSn Tr Tc1 T1 CKIO CS2 or CS3 RAS CAS RD WR DQM WEn CSn a Burst write mode b Single write mode Synchronous DRAM write access Synchronous DRAM write access Normal space access Normal space access Figure 7 61 Normal Space Access Immediately after Synchronous DRAM Write ...

Page 382: ... be set Set a value other than the initial value in bits AnSHW1 AnSHW0 A4HW1 and A4HW0 for the relevant space 7 11 3 When connecting external device to synchronous DRAM When connecting an external device to the synchronous DRAM not only CSnN and DACKn but also other instructions for the synchronous DRAM such as CSnN RASN CASN and RDWRN must be recognized for the estimation of an access sequence In...

Page 383: ...Four 32 bit accesses are required to update a line Since the number of entries is 64 the six bits A9 to A4 in each address determine the entry A four way set associative configuration is used so up to four different instructions data can be stored in the cache even when entry addresses match To efficiently use four ways having the same entry address replacement is provided based on a pseudo LRU le...

Page 384: ...register CCR R W H 00 H FFFFFE92 8 2 Register Description 8 2 1 Cache Control Register CCR The cache control register CCR is used for cache control CCR must be set and the cache must be initialized before use CCR is initialized to H 00 by a power on reset or manual reset Bit 7 6 5 4 3 2 1 0 W1 W0 WB CP TW OD ID CE Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 7 and 6 Way S...

Page 385: ... mode bit The cache operates as a four way set associative cache when TW is 0 and as a two way set associative cache and 2 kbyte RAM when TW is 1 In the two way mode ways 2 and 3 are cache and ways 0 and 1 are RAM Ways 0 and 1 are read or written by direct access of the data array according to address space specification Bit 3 TW Description 0 Four way mode Initial value 1 Two way mode Bit 2 Data ...

Page 386: ...sabled Initial value 1 Cache enabled 8 3 Address Space and the Cache The address space is divided into six partitions The cache access operation is specified by addresses Table 8 2 lists the partitions and their cache operations For more information on address spaces see section 7 Bus State Controller Note that the spaces of the cache area and cache through area are the same Table 8 2 Address Spac...

Page 387: ...e miss Tag addresses of entries with valid bits of 0 will not match in any case When a cache hit occurs data is read from the data array of the way that was matched according to the entry address the byte address within the line and the access data size and is sent to the CPU The address output on the cache address bus is calculated in the CPU s instruction execution phase and the results of the r...

Page 388: ...ented by 4 so that the longword that contains the address to be read from the cache comes last The read data on the internal data bus is written sequentially to the cache data array One cycle after the last data is written to the cache data array it is also output to the cache data bus and the read data is sent to the CPU The internal address bus and internal data bus also function as pipelines ju...

Page 389: ...ay If they do not match nothing is written to the cache data array The write address is output to the internal address bus 1 cycle later than the cache address bus The write data is similarly output to the internal data bus 1 cycle later than the cache data bus The CPU waits until the writes on the internal buses are completed figure 8 5 Address A CPU pipeline stage Iφ Cache address bus Cache data...

Page 390: ... cache miss occurs the way for replacement is determined using the LRU information and the write address from the CPU is written in the address array for that way Simultaneously the valid bit and update bit are set to 1 Since the 16 bytes of data for replacing the data array are simultaneously read when the data on the cache bus is written to the cache the address on the cache address bus is outpu...

Page 391: ...ack to external memory is necessary To improve performance the entry to be replaced is first transferred to the write back buffer and fetching of the new entry into the cache is given priority over the write back When the new entry has been fetched into the cache the write back buffer contents are written back to external memory The cache can be accessed during this write back The write back buffe...

Page 392: ...s bus Internal data bus MA WB EX MA Address A Address A Address B Address A Address A EX Instruction execution MA Memory access WB Write back Figure 8 9 Reading Cache Through Areas 8 4 4 The TAS Instruction The TAS instruction reads data from memory compares it to 0 reflects the result in the T bit of the status register SR and sets the most significant bit to 1 It is an instruction that writes to...

Page 393: ...1 way 0 Thereafter the way is selected according to the order of access in the program Since the replacement will not be correct if the LRU gets an inappropriate value the address array write function can be used to rewrite When this is done be sure not to write a value other than 0 as the LRU information When the OD bit or ID bit in CCR is 1 cache replacement is not performed even if a cache miss...

Page 394: ...s required for writing to CCR Always initialize the valid bit and LRU before enabling the cache When the cache is enabled instructions are read from the cache even during writing to CCR This means that the prefetched instructions are read from the cache To do a proper purge write 0 to CCR s CE bit then disable the cache and purge Since CCR s CE bit is cleared to 0 by a power on reset or manual res...

Page 395: ... DMAC or DMAC The chip does not support an instruction or procedure for flushing the contents of specific addresses so in order to execute a cache flush it is necessary to perform reads in a 4 kbyte space cache area other than the address space to be flushed from cache and intentionally create cache misses For this purpose cache accesses should be performed every 16 bytes By this means write backs...

Page 396: ...e BA Byte address within line W Way specification Address Bit Number of bits Bit Number of bits Figure 8 12 Data Array Access 8 4 10 Address Array Access The address array of the cache can be accessed so that the contents fetched to the cache can be checked for purposes of program debugging or the like The address array is mapped on H 60000000 to H 600003FF Since all of the ways are mapped to the ...

Page 397: ...ber of bits Figure 8 13 Address Array Access 8 5 Cache Use 8 5 1 Initialization Cache memory is not initialized in a reset Therefore the cache must be initialized by software before use The cache is initialized by zeroizing all address array valid bits and LRU information The address array write function can be used to initialize each line but it is simpler to initialize it once by writing 1 to th...

Page 398: ...g 32 bytes from address R3 MOV L H 40000000 R0 XOR R1 R1 MOV L R1 R0 R3 ADD 16 R3 MOV L R1 R0 R3 Figure 8 15 Purging Specific Addresses When it is troublesome to purge the cache after every DMA transfer it is recommended that the OD bit in CCR be set to 1 in advance When the OD bit is 1 the cache operates as cache memory only for instructions However when data is already fetched into cache memory ...

Page 399: ...hen the update unit is larger it is faster to purge the entire cache rather than purging all the addresses in order and then read the data that previously existed in the cache again from external memory When write back is used coherency can be maintained by executing write backs flushing to memory by means of intentional cache miss reads but since executing flushing incurs an overhead use of write...

Page 400: ...ring the standby mode for power down operation After returning from standby initialize the cache before use 8 6 2 Cache Control Register Changing the contents of CCR also changes cache operation The chip makes full use of pipeline operations so it is difficult to synchronize access For this reason change the contents of the cache control register simultaneously when disabling the cache or after th...

Page 401: ...ansmission and reception of Ethernet IEEE802 3 frames The Ethernet controller is connected to dedicated transmit and receive Ethernet DMACs E DMACs in the SH7616 and carries out high speed data transfer to and from memory 9 1 1 Features The EtherC has the following features Transmission and reception of Ethernet IEEE802 3 frames Supports 10 100 Mbps transfer Supports full duplex and half duplex mo...

Page 402: ... stored in the transmit FIFO from memory via the transmit E DMAC The transmit controller assembles this data into an Ethernet IEEE802 3 frame which it outputs to the MII After passing through the MII the transmit data is sent onto the line by a PHY LSI The main functions of the transmit controller are as follows Frame assembly and transmission CRC calculation and provision to frames Data retransmi...

Page 403: ...f the receive controller are as follows Checking received frame format Checking receive frame CRC and frame length Transfer of own address multicast or broadcast receive frames to memory Compliant with MII in IEEE802 3u standard Nibble byte conversion supporting PHY LSI speed Magic Packet monitoring CAM Content Addressable Memory match signal input function Command Status Interface This interface ...

Page 404: ... 4 bit transmit data TX ER Transmit error Output Notifies PHY LSI of error during transmission RX DV Receive data valid Input Indicates that there is valid receive data on ERXD0 to ERXD3 ERXD0 ERXD3 Receive data 4 bit Input 4 bit receive data RX ER Receive error Input Identifies error state occurring during data reception CRS Carrier detect Input Carrier detection signal COL Collision detect Input...

Page 405: ...ollision detect counter register SCDCR R W 2 H 00000000 H FFFFFDB4 Delay Collision detect counter register CDCR R W 2 H 00000000 H FFFFFD84 Lost carrier counter register LCCR R W 2 H 00000000 H FFFFFD88 Carrier not detect counter register CNDCR R W 2 H 00000000 H FFFFFD8C Illegal frame length counter register IFLCR R W 2 H 00000000 H FFFFFD90 CRC error frame receive counter register CEFCR R W 2 H ...

Page 406: ...his register are normally made in the initialization process following a reset Notes Operation mode settings must not be changed while the transmitting and receiving functions are enabled To modify bits other than the ECMR s RE and TE bits follow the procedures below 1 Return EtherC and E DMAC to their initial state by means of the software reset bit SWR in the E DMAC mode register EDMR and make n...

Page 407: ... register and the WOL pin notifies peripheral LSIs that the Magic Packet has been received Bit 9 MPDE Description 0 Magic Packet detection is not enabled Initial value 1 Magic Packet detection is enabled Bits 8 and 7 Reserved These bits are always read as 0 The write value should always be 0 Bit 6 Receiver Enable RE Enables or disables the receiver Bit 6 RE Description 0 Receiver is disabled Initi...

Page 408: ...using the EXOUT pin Bit 2 ELB Description 0 Low level output from EXOUT pin Initial value 1 High level output from EXOUT pin Note In order for PHY loopback to be implemented using this function the PHY LSI must have a pin corresponding to the EXOUT pin Bit 1 Duplex Mode DM Specifies the EtherC transfer method Bit 1 DM Description 0 Half duplex transfer is specified Initial value 1 Full duplex tran...

Page 409: ...re always read as 0 The write value should always be 0 Bit 2 LINK Signal Changed LCHNG Indicates that the LNKSTA signal input from the PHY LSI has changed from high to low or from low to high This bit is cleared by writing 1 to it Writing 0 to this bit has no effect Bit 2 LCHNG Description 0 LNKSTA signal change has not been detected Initial value 1 LNKSTA signal change high to low or low to high ...

Page 410: ...LSI used 9 2 3 EtherC Interrupt Permission Register ECSIPR Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 LCHNGI P MPDIP ICDIP Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W This register enables or disables the interrupt sources indicated by the EtherC status register Each bit in this register enables or disables the interrupt indicated by the co...

Page 411: ...ed Initial value 1 Interrupt notification by ICD bit in ECSR is enabled 9 2 4 PHY Interface Register PIR Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 MDI MDO MMD MDC Initial value 0 0 0 0 0 0 0 R W R R R R R R W R W R W Note Undefined PIR provides a means of accessing PHY LSI internal registers via the MII Bits 31 to 4 Reserved These bits are always read...

Page 412: ...MA30 MA29 MA28 MA27 MA26 MA25 MA24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 MA23 MA22 MA21 MA20 MA19 MA18 MA17 MA16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The upper 32 bits of the 48 bit MAC address are set in MARH The setting in this register is normally made in the initialization process after a reset Note The MAC address se...

Page 413: ... MAC address are set in MARL The setting in this register is normally made in the initialization process after a reset Note The MAC address setting must not be changed while the transmitter and receiver are enabled First return the EtherC and E DMAC modules to their initial state by means of the SWR bit in the E DMAC mode register EDMR then make the new setting Bits 31 to 16 Reserved These bits ar...

Page 414: ...rame length in bytes that can be received by the SH7616 Bits 31 to 12 Reserved These bits are always read as 0 The write value should always be 0 Bits 11 to 0 Receive Frame Length RFL H 000 H 5EE 1 518 bytes H 5EF 1 519 bytes H 5F0 1 520 bytes H 7FF 2 047 bytes H 800 H FFF 2 048 bytes Notes 1 The frame length refers to all fields from the destination address up to and including the CRC data 2 When...

Page 415: ... R R PSR enables interface signals from the PHY LSI to be read Bits 31 to 1 Reserved These bits are always read as 0 The write value should always be 0 Bit 0 Link Monitor LMON The link status can be read by connecting the LINK signal output from the PHY LSI For information on the polarity refer to the specifications for the PHY LSI to be connected Note The LMON bit is set to 0 when the LNKSTA pin ...

Page 416: ...R W R W R W R W R W R W R W R W R W TROCR is a 16 bit counter that indicates the number of frames that were unable to be transmitted in 16 retransmission attempts When 16 transmission attempts have failed TROCR is incremented by 1 When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bit...

Page 417: ...COSDC27 COSDC26 COSDC25 COSDC24 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 23 22 21 20 19 18 17 16 COSDC23 COSDC22 COSDC21 COSDC20 COSDC19 COSDC18 COSDC17 COSDC16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 COSDC15 COSDC14 COSDC13 COSDC12 COSDC11 COSDC10 COSDC9 COSDC8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R ...

Page 418: ...C0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W CDCR is a 16 bit counter that indicates the number of collisions that occurred on the line counting from a point 512 bits after the start of data transmission When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 3...

Page 419: ...C3 LCC2 LCC1 LCC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W LCCR is a 16 bit counter that indicates the number of times the carrier was lost during data transmission When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Reserved These bits are always...

Page 420: ...DC3 CNDC2 CNDC1 CNDC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W CNDCR is a 16 bit counter that indicates the number of times the carrier could not be detected while the preamble was being sent When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Res...

Page 421: ...nitial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W IFLCR is a 16 bit counter that indicates the number of times transmission of a packet with a frame length of less than four bytes was attempted during data transmission When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial ...

Page 422: ... R W R W R W R W R W R W CEFCR is a 16 bit counter that indicates the number of times a frame with a CRC error was received When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Reserved These bits are always read as 0 The write value should always be 0 Bits 15 to 0 CRC Err...

Page 423: ...alue 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W FRECR is a 16 bit counter that indicates the number of frames input from the PHY LSI for which a receive error was indicated by the RX ER pin FRECR is incremented each time this pin becomes active When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write ...

Page 424: ...TSFC3 TSFC2 TSFC1 TSFC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W TSFRCR is a 16 bit counter that indicates the number of frames of fewer than 64 bytes that have been received When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Reserved These bits ...

Page 425: ...ing the value specified by the receive frame length register RFLR When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Reserved These bits are always read as 0 The write value should always be 0 Bits 15 to 0 Too Long Frame Receive Count 15 to 0 TLFC15 to TLFC0 These bits i...

Page 426: ...3 RFC2 RFC1 RFC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W RFCR is a 16 bit counter that indicates the number of frames received containing residual bits less than an 8 bit unit When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Reserved These bit...

Page 427: ...C6 MAFC5 MAFC4 MAFC3 MAFC2 MAFC1 MAFC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W MAFCR is a 16 bit counter that indicates the number of frames received with a multicast address specified When the value in this register reaches H FFFF 65 535 the count is halted The counter value is cleared to 0 by a write to this register the write value is immaterial Bits 31 to 16 Reserved ...

Page 428: ...ion is performed continuously in combination with the E DMACs For details of continuous operation see the description of E DMAC operation 2 The receive data transferred to memory by the receive data E DMAC does not include CRC data 9 3 1 Transmission The main transmit functions of the EtherC are as follows Frame generation and transmission Monitors the line status then adds the preamble SFD and CR...

Page 429: ...ased on the back off algorithm 2 Transmission is retried only when data of 512 bits or less including the preamble and SFD is transmitted When a collision is detected during the transmission of data greater than 512 bits only jam is transmitted and transmission based on the back off algorithm is not retried Collision 2 Collision 2 Figure 9 2 EtherC Transmitter State Transitions 1 When the transmit...

Page 430: ...e E DMAC The main receive functions of the EtherC are as follows Receive frame header check Checks the preamble and SFD and discards a frame with an invalid pattern Receive frame data check Checks the data length in the header and reports an error status if the data length is less than 64 bytes or greater than the specified number of bytes Receive CRC check Performs a CRC check on the frame data f...

Page 431: ...ception CRC reception Wait for SFD reception Figure 9 3 EtherC Receiver State Transitions 1 When the receive enable RE bit is set the receiver enters the receive idle state 2 When an SFD start frame delimiter is detected after a receive packet preamble the receiver starts receive processing 3 If the destination address matches the receiver s own address or if broadcast or multicast transmission or...

Page 432: ...llision during transmission in figure 9 4 b and the timing in the case of an error during transmission in figure 9 4 c The normal timing for frame reception is shown in figure 9 4 d and the timing in the case of errors during transmission in figures 9 4 e and f TX CLK TX EN TXD3 TXD0 TX ER CRS COL SFD Preamble Data CRC Figure 9 4 a MII Frame Transmit Timing Normal Transmission TX CLK TX EN TXD3 TX...

Page 433: ... 4 c MII Frame Transmit Timing Transmit Error RX CLK RX DV RXD3 RXD0 RX ER Preamble Data CRC SFD Figure 9 4 d MII Frame Receive Timing Normal Reception RX CLK RX DV RXD3 RXD0 RX ER Preamble Data XXXX SFD Figure 9 4 e MII Frame Receive Timing Receive Error 1 RX CLK RX DV RXD3 RXD0 RX ER XXXX 1110 XXXX Figure 9 4 f MII Frame Receive Timing Receive Error 2 ...

Page 434: ...te of 0001 if the PHY LSI address is 1 sequential write starting with the MSB This bit changes depending on the PHY LSI address REGAD Write of 0001 if the register address is 1 sequential write starting with the MSB This bit changes depending on the PHY LSI register address TA Time for switching data transmission source on MII interface a Write 10 written b Read Bus release notation Z0 performed D...

Page 435: ...9 6 d MDC MDO 1 bit data write timing relationship 1 Write to PHY interface register MMD 1 MDO write data MDC 0 2 Write to PHY interface register MMD 1 MDO write data MDC 1 3 Write to PHY interface register MMD 1 MDO write data MDC 0 1 2 3 Figure 9 6 a 1 Bit Data Write Flowchart MDC MDO Bus release timing relationship 1 Write to PHY interface register MMD 0 MDC 0 2 Write to PHY interface register ...

Page 436: ...ter MMD 0 MDC 1 2 Read from PHY interface register read MMD 0 MMC 1 MDI is read data 3 Write to PHY interface register MMD 0 MDC 0 MDC MDI 1 3 2 Figure 9 6 c 1 Bit Data Read Flowchart Independent bus release timing relationship 1 Write to PHY interface register MMD 0 MDC 0 MDC MDO 1 Figure 9 6 d Independent Bus Release Flowchart IDLE in Write in Figure 9 5 ...

Page 437: ... the EtherC mode register ECMR 3 Set the Magic Packet detection interrupt enable bit MPDIP in the EtherC interrupt enable register ECSIPR to the enable setting 4 If necessary set the CPU operating mode to sleep mode or set supporting functions to module standby mode 5 When a Magic Packet is detected an interrupt is sent to the CPU The WOL pin notifies peripheral LSIs that the Magic Packet has been...

Page 438: ...means of a magic packet supporting function interrupt sources should be masked before sleep mode is entered See section 9 3 5 Magic Packet Detection for the setting procedure Standby Mode In standby mode the on chip oscillation circuit is halted Consequently the clock is not supplied to the EtherC and interrupts from the EtherC and other supporting modules cannot be reported It is therefore not po...

Page 439: ...rded in the two states of the CAMSEN signal The CAM holds the MAC address besides this LSI When the MAC address which is received from the PHY LSI is matched with the destination address held in the CAM the CAMSEN signal is asserted The EtherC recognizes that the CAMSEN signal has been asserted then receives a frame for the reception Some of the frame s data will have already been stored in the re...

Page 440: ...es CAMSEN Input Frame Type Normal Mode Promise CAS Mode Asserted SH7616 MAC address Discarded Discarded address is Broadcast address Discarded Discarded matched Multicast address Discarded Discarded CAM MAC addresses Received Discarded Negated SH7616 MAC address Received Received address is not Broadcast address Received Received matched Multicast address Received Received CAM MAC addresses Discar...

Page 441: ... Devices Inc Figure 9 10 shows example of connection to a DP83843 National Semiconductor Corporation TX ER ETXD3 ETXD2 ETXD1 ETXD0 TX EN TX CLK MDC MDIO ERXD3 ERXD2 ERXD1 ERXD0 RX CLK CRS COL RX DV RX ER TXER ETXD3 ETXD2 ETXD1 ETXD0 TXEN TXCLK MDC MDIO ERXD3 ERXD2 ERXD1 ERXD0 RXCLK CRS COL RXDV RXER SH7616 AM79C873 MII Media independent interface Figure 9 9 Example of Connection to AM79C873 ...

Page 442: ... TX ER ETXD3 ETXD2 ETXD1 ETXD0 TX EN TX CLK MDC MDIO ERXD3 ERXD2 ERXD1 ERXD0 RX CLK CRS COL RX DV RX ER TX_ER TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK MDC MDIO RXD3 RXD2 RXD1 RXD0 RX_CLK CRS COL RX_DV RX_ER SH7616 DP83843 MII Media independent interface Figure 9 10 Example of Connection to DP83843 ...

Page 443: ...tion of buffer management is controlled by the E DMAC itself using descriptors This lightens the load on the CPU and enables efficient data transfer control to be achieved 10 1 1 Features The E DMAC has the following features The load on the CPU is reduced by means of a descriptor management system Transmit receive frame status information is indicated in descriptors Achieves efficient system bus ...

Page 444: ...tion of the E DMAC and the descriptors and transmit receive buffers in memory SH7616 E DMAC Internal bus interface EtherC Descriptor information Transmit DMAC Descriptor information Receive DMAC External bus interface Tx FIFO Rx FIFO Transmit descriptors Transmit buffer Receive descriptors Receive buffer Memory Figure 10 1 Configuration of E DMAC and Descriptors and Buffers ...

Page 445: ...ansmit FIFO In this way continuous data transmission can be carried out Reception For each start of a receive DMA transfer the receive E DMAC fetches a receive buffer address from the top of the receive descriptor list When receive data is stored in the receive FIFO the E DMAC transfers this data to the receive buffer When reception of one frame is finished the E DMAC performs a receive status wri...

Page 446: ...nterrupt permission register EESIPR R W H 00000000 H FFFFFD18 Transmit receive status copy enable register TRSCER R W H 00000000 H FFFFFD1C Receive missed frame counter register RMFCR R W 2 H 00000000 H FFFFFD20 Transmit FIFO threshold register TFTR R W H 00000000 H FFFFFD24 FIFO depth register FDR R W H 00000000 H FFFFFD28 Receiver control register RCR R W H 00000000 H FFFFFD2C E DMAC operation c...

Page 447: ...irst return the EtherC and E DMAC modules to their initial state by means of the software reset bit SWR in this register then make new settings Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 DL1 DL0 SWR Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R R R R W Bits 31 to 6 Reserved These bits are always read as 0 The write value should always be 0 Bits 5 and...

Page 448: ... issues transmit directives to the E DMAC Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 TR Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bits 31 to 1 Reserved These bits are always read as 0 The write value should always be 0 Bit 0 Transmit Request TR When 1 is written to this bit the E DMAC reads a descriptor and in the case of an active descriptor...

Page 449: ...ceive requests from the EtherC Bit 0 RR Description 0 After frame reception is completed the receiver is disabled 1 A receive descriptor is read and transfer is enabled Notes In order to receive a frame in response to a receive request the receive descriptor active bit in the receive descriptor must be set to active beforehand 1 When the receive request bit is set the E DMAC reads the relevant rec...

Page 450: ...7 TDLA16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 TDLA15 TDLA14 TDLA13 TDLA12 TDLA11 TDLA10 TDLA9 TDLA8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 TDLA7 TDLA6 TDLA5 TDLA4 TDLA3 TDLA2 TDLA1 TDLA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 31 to 0 Transmit Descriptor Start Addres...

Page 451: ...LA20 RDLA19 RDLA18 RDLA17 RDLA16 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 RDLA15 RDLA14 RDLA13 RDLA12 RDLA11 RDLA10 RDLA9 RDLA8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 RDLA7 RDLA6 RDLA5 RDLA4 RDLA3 RDLA2 RDLA1 RDLA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 31 to 0 Receive ...

Page 452: ... Bit 15 14 13 12 11 10 9 8 ITF CND DLC CD TRO Initial value 0 0 0 0 0 0 0 0 R W R R R R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 RMAF RFAR RRF RTLF RTSF PRE CERF Initial value 0 0 0 0 0 0 0 0 R W R W R R W R W R W R W R W R W Bits 31 to 25 Reserved These bits are always read as 0 The write value should always read as 0 Bit 24 Receive Frame Counter Overflow RFCOF Indicates that the receive FIFO frame ...

Page 453: ... frame is transmitted and the transmission descriptor valid bit TACT in the next descriptor is not set for multiple frame buffer processing transmission is completed and this bit is set to 1 After frame transmission the E DMAC writes the transmission status back to the descriptor Bit 21 TC Description 0 Transfer not complete or no transfer directive Initial value 1 Transfer complete interrupt sour...

Page 454: ...e 1 Frame received interrupt source Bit 17 Receive Descriptor Exhausted RDE This bit is set if the receive descriptor active bit RACT setting is inactive RACT 0 when the E DMAC reads a receive descriptor Bit 17 RDE Description 0 1 receive descriptor active bit RACT detected Initial value 1 0 receive descriptor active bit RACT detected interrupt source Note When receive descriptor empty RDE 1 occur...

Page 455: ...cted interrupt source Bit 10 Detect Loss of Carrier DLC Indicates that loss of the carrier has been detected during frame transmission Bit 10 DLC Description 0 Loss of carrier not detected Initial value 1 Loss of carrier detected interrupt source Bit 9 Collision Detect CD Indicates that a collision has been detected during frame transmission Bit 9 CD Description 0 Collision not detected Initial va...

Page 456: ... RFAR Description 0 Receive frame discard request assertion has not been received Initial value 1 Receive frame discard request assertion has been received interrupt source Bit 4 Receive Residual Bit Frame RRF Indicates that a residual bit frame has been received Bit 4 RRF Description 0 Residual bit frame has not been received Initial value 1 Residual bit frame has been received interrupt source B...

Page 457: ... error notification from the MII PHY LSI Bit 1 PRE Description 0 PHY LSI receive error not detected Initial value 1 PHY LSI receive error detected interrupt source Bit 0 CRC Error on Received Frame CERF Indicates that a CRC error has been detected in the received frame Bit 0 CERF Description 0 CRC error not detected Initial value 1 CRC error detected interrupt source ...

Page 458: ...ECIIP TCIP TDEIP TFUFIP FRIP RDEIP RFOFIP Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 ITFIP CNDIP DLCIP CDIP TROIP Initial value 0 0 0 0 0 0 0 0 R W R R R R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 RMAFIP RFARIP RRFIP RTLFIP RTSFIP PREIP CERFIP Initial value 0 0 0 0 0 0 0 0 R W R W R R W R W R W R W R W R W Bits 31 to 25 Reserved These bits are always rea...

Page 459: ...e interrupt is disabled Initial value 1 Frame transmit complete interrupt is enabled Bit 20 Transmit Descriptor Exhausted Interrupt Permission TDEIP Enables the transmit descriptor exhausted interrupt Bit 20 TDEIP Description 0 Transmit descriptor exhausted interrupt is disabled Initial value 1 Transmit descriptor exhausted interrupt is enabled Bit 19 Transmit FIFO Underflow Interrupt Permission T...

Page 460: ...nterrupt is enabled Bits 15 to 13 Reserved These bits are always read as 0 The write value should always be 0 Bit 12 Illegal Transmit Frame Interrupt Permission ITFIP Enables the illegal transmit frame interrupt Bit 12 ITFIP Description 0 Illegal transmit frame interrupt is disabled Initial value 1 Illegal transmit frame interrupt is enabled Bit 11 Carrier Not Detect Interrupt Permission CNDIP Ena...

Page 461: ...the receive multicast address frame interrupt Bit 7 RMAFIP Description 0 Receive multicast address frame interrupt is disabled Initial value 1 Receive multicast address frame interrupt is enabled Bits 6 Reserved This bit is always read as 0 The write value should always be 0 Bit 5 Receive Frame Discard Request Assertion Interrupt Permission RFARIP Enables the receive frame discard request assertio...

Page 462: ...o short frame interrupt Bit 2 RTSFIP Description 0 Receive too short frame interrupt is disabled Initial value 1 Receive too short frame interrupt is enabled Bit 1 PHY LSI Receive Error Interrupt Permission PREIP Enables the PHY LSI receive error interrupt Bit 1 PREIP Description 0 PHY LSI receive error interrupt is disabled Initial value 1 PHY LSI receive error interrupt is enabled Bit 0 CRC Erro...

Page 463: ...of the corresponding source is not indicated in the descriptor After the chip is reset all bits are cleared to 0 Bit 31 30 29 19 18 17 16 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 RMAFCE Initial value 0 0 0 0 0 0 0 0 R W R W R R R R R R R Bits 31 to 8 Reserved These bits are always read as 0 The wri...

Page 464: ...es in the FIFO are discarded The number of frames discarded at this time are counted When the value in this register reaches H FFFF 65 535 the count is halted When this register is read the counter value is cleared to 0 Writes to this register have no effect Bit 31 30 29 19 18 17 16 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 15 14 13 12 11 10 9 8 MFC15 MFC14 MFC13 MFC12 MFC11 MFC10 MFC9 MFC...

Page 465: ...e transmit FIFO exceeds the number of bytes specified by this register when the transmit FIFO is full or when 1 frame write is executed Note When setting this register do so in the transmission halt state Bit 31 30 29 19 18 17 16 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 15 14 13 12 11 10 9 8 TFT10 TFT9 TFT8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Bit 7 6 5 4 3 2 1 0 TFT7 T...

Page 466: ...e and forward mode transmission starts when one frame of data is written or transmit FIFO is full Initial value H 01 4 bytes H 02 8 bytes H 1F 124 bytes H 20 128 bytes H 3F 252 bytes H 40 256 bytes H 7F 508 bytes H 80 512 bytes H FF 1023 bytes H 100 1024 bytes H 1FF 2047 bytes H 200 2048 bytes Note Note When setting a transmit FIFO the FIFO must be set to a smaller value than the specified value o...

Page 467: ...R R W R W R W Bit 7 6 5 4 3 2 1 0 RFD2 RFD1 RFD0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Bits 31 to 11 Reserved These bits are always read as 0 The write value should always be 0 Bit 10 to 8 Transmit FIFO Depth TFD Specifies 256 bytes to 2 kbytes in 256 byte units as the depth size of the transmit FIFO The setting cannot be changed after transmission reception has started Bits 10 t...

Page 468: ...when a frame is received Note When setting this register do so in the receiving halt state Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 RNC Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R W Bits 31 to 1 Reserved These bits are always read as 0 The write value should always be 0 Bit 0 Receive Enable Control RNC Bit 0 RNC Description 0 When reception of ...

Page 469: ...ow occurs Bit 3 FEC Description 0 E DMAC operation continues when underflow or overflow occurs Initial value 1 E DMAC operation halts when underflow or overflow occurs Bit 2 Address Error Control AEC Indicates detection of an illegal memory address in an attempted E DMAC transfer Bit 2 AEC Description 0 Illegal memory address not detected normal operation Initial value 1 Illegal memory address det...

Page 470: ...egister Bit 31 30 29 28 27 26 25 24 RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA25 RBWA24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA17 RBWA16 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 RBWA15 RBWA14 RBWA13 RBWA12 RBWA11 RBWA10 RBWA9 RBWA8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R ...

Page 471: ...5 24 RDFA31 RDFA30 RDFA29 RDFA28 RDFA27 RDFA26 RDFA25 RDFA24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 RDFA23 RDFA22 RDFA21 RDFA20 RDFA19 RDFA18 RDFA17 RDFA16 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 RDFA15 RDFA14 RDFA13 RDFA12 RDFA11 RDFA10 RDFA9 RDFA8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 RDFA7...

Page 472: ...TBRA31 TBRA30 TBRA29 TBRA28 TBRA27 TBRA26 TBRA25 TBRA24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 TBRA23 TBRA22 TBRA21 TBRA20 TBRA19 TBRA18 TBRA17 TBRA16 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 TBRA15 TBRA14 TBRA13 TBRA12 TBRA11 TBRA10 TBRA9 TBRA8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 TBRA7 TBRA...

Page 473: ...6 25 24 TDFA31 TDFA30 TDFA29 TDFA28 TDFA27 TDFA26 TDFA25 TDFA24 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 23 22 21 20 19 18 17 16 TDFA23 TDFA22 TDFA21 TDFA20 TDFA19 TDFA18 TDFA17 TDFA16 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 15 14 13 12 11 10 9 8 TDFA15 TDFA14 TDFA13 TDFA12 TDFA11 TDFA10 TDFA9 TDFA8 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 TD...

Page 474: ... and receive descriptor lists in memory The start addresses of these lists are then set in the transmit and receive descriptor list start address registers Transmit Descriptor Figure 10 2 shows the relationship between a transmit descriptor and the transmit buffer According to the specification in this descriptor the relationship between the transmit frame and transmit buffer can be defined as one...

Page 475: ...is recognized in an E DMAC descriptor read the E DMAC terminates transmit processing and transmit operations cannot be continued a restart is necessary 1 The transmit descriptor is valid Indicates that valid data has been written to the transmit buffer by the CPU and frame transfer processing has not yet been executed or that frame transfer is in progress When this state is recognized in an E DMAC...

Page 476: ... the TDLE bit Bit 27 Transmit Frame Error TFE Indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set Bit 27 TFE Description 0 No error during transmission 1 An error of some kind occurred during transmission see bits 26 to 0 Bits 26 to 0 Transmit Frame Status 26 to 0 TFS26 to TFS0 These bits indicate the error status during frame transmission TFS26 to TFS9 Re...

Page 477: ...byte boundary Bits 31 to 0 Transmit Buffer Address TBA Receive Descriptor Figure 10 3 shows the relationship between a receive descriptor and the receive buffer In frame reception the E DMAC performs data rewriting up to a receive buffer 16 byte boundary regardless of the receive frame length Finally the actual receive frame length is reported in the lower 16 bits of RD1 in the descriptor Data tra...

Page 478: ... receive frame processing the CPU sets this bit to prepare for reception Bit 31 RACT Description 0 The receive descriptor is invalid Indicates that the receive buffer is not ready access disabled by E DMAC or this bit has been reset by a write back operation on termination of E DMAC frame transfer processing completion or suspension of reception If this state is recognized in an E DMAC descriptor ...

Page 479: ...his descriptor continues frame is not concluded 1 Receive buffer indicated by this descriptor contains end of frame frame is concluded 1 0 Receive buffer indicated by this descriptor is start of frame frame is not concluded 1 Contents of receive buffer indicated by this descriptor are equivalent to one frame one frame one buffer Bit 27 Receive Frame Error RFE Indicates that one or other bit of the...

Page 480: ...o 16 Receive Buffer Length RBL These bits specify the maximum transfer byte length in the corresponding receive buffer Notes The transfer byte length must align with a 16 byte boundary bits 19 to 16 cleared to 0 The maximum receive frame length with one frame per buffer is 1 514 bytes excluding the CRC data Therefore for the receive buffer length specification a value of 1 520 bytes H 05F0 that ta...

Page 481: ...t buffer start address specified by TD2 and transfers it to the EtherC The EtherC creates a transmit frame and starts transmission to the MII After DMA transfer of data equivalent to the buffer length specified in the descriptor the following processing is carried out according to the TFP value 1 TFP 00 or 01 frame continuation Descriptor write back is performed after DMA transfer 2 TFP 01 or 11 f...

Page 482: ...ssion flowchart E DMAC EtherC Ethernet Transmit FIFO EtherC E DMAC initialization Descriptor and transmit buffer setting Transmit directive Descriptor read Descriptor write back Descriptor write back Transmission completed Descriptor read Transmit data transfer Transmit data transfer Frame transmission Figure 10 4 Sample Transmission Flowchart ...

Page 483: ...he frame to the receive buffer specified by RD2 If the data length of the received frame is greater than the buffer length given by RD1 the E DMAC performs write back to the descriptor when the buffer is full RFP 10 or 00 then reads the next descriptor The E DMAC then continues to transfer data to the receive buffer specified by the new RD2 When frame reception is completed or if frame reception i...

Page 484: ... EtherC Receive FIFO Ethernet EtherC E DMAC initialization Descriptor and transmit buffer setting Reception completed Receive data transfer Frame reception Start of reception Descriptor read Descriptor write back Descriptor write back Descriptor read preparation for receiving next frame Descriptor read Receive data transfer Figure 10 5 Sample Reception Flowchart ...

Page 485: ...descriptor not only is the TACT bit cleared to 0 but write back is also performed to the TFE and TFS bits at the same time Data in the buffer is not transmitted between the occurrence of an error and write back to the final descriptor If error interrupts are enabled in the EtherC E DMAC status interrupt permission register EESIPR an interrupt is generated immediately after the final descriptor wri...

Page 486: ...are enabled in the EtherC E DMAC status interrupt permission register EESIPR an interrupt is generated immediately after the write back If there is a new frame receive request reception is continued from the buffer after that in which the error occurred 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E DMAC Inactivates RACT and writes RFE RFS Descriptor read Write back Desc...

Page 487: ...y four longword writes Maximum of 16 777 216 16M transfers In the event of a cache hit CPU instruction processing and DMA operation can be executed in parallel Single address mode transfers Either the transfer source or transfer destination peripheral device is accessed by a DACK signal selectable while the other is accessed by address One transfer unit of data is transferred in one bus cycle Poss...

Page 488: ... and external memory Transfer requests External request from the DREQn pins Edge or level detection and active low or active high mode can be specified for DREQn On chip peripheral module requests serial communication interface with FIFO SCIF 16 bit timer pulse unit TPU serial I O with FIFO SIOF serial I O SIO Auto request the transfer request is generated automatically within the DMAC Choice of b...

Page 489: ...s controller Iteration control Register control Start up control Request priority control Interrupt control Bus interface DMAC module bus SARn DARn TCRn CHCRn DMAOR VCRDMAn Internal bus DMAOR SARn DARn TCRn CHCRn VCRDMAn DEIn On chip peripheral module request BH n DMA operation register DMA source address register DMA destination address register DMA transfer count register DMA channel control reg...

Page 490: ...st DREQ0 I DMA transfer request input from external device to channel 0 DMA transfer request acknowledge DACK0 O DMA transfer request acknowledge output from channel 0 to external device 1 DMA transfer request DREQ1 I DMA transfer request input from external device to channel 1 DMA transfer request acknowledge DACK1 O DMA transfer request acknowledge output from channel 1 to external device All Bu...

Page 491: ...mber register 0 VCRDMA0R W Undefined H FFFFFFA0 32 DMA request response selection control register 0 DRCR0 R W H 00 H FFFFFE71 8 3 1 DMA source address register 1 SAR1 R W Undefined H FFFFFF90 32 DMA destination address register 1 DAR1 R W Undefined H FFFFFF94 32 DMA transfer count register 1 TCR1 R W Undefined H FFFFFF98 32 DMA channel control register 1 CHCR1 R W 1 H 00000000 H FFFFFF9C 32 DMA v...

Page 492: ... retained in a reset in standby mode and when the module standby function is used 11 2 2 DMA Destination Address Registers 0 and 1 DAR0 DAR1 Bit 31 30 29 3 2 1 0 Initial value R W R W R W R W R W R W R W R W DMA destination address registers 0 and 1 DAR0 and DAR1 are 32 bit read write registers that specify the destination address of a DMA transfer During a DMA transfer these registers indicate th...

Page 493: ...77 216 the maximum when H 00000000 is set During a DMA transfer these registers indicate the remaining transfer count Set the initial value as the write value in the upper eight bits These bits always read 0 Values are retained in a reset in standby mode and when the module standby function is used For 16 byte transfers set the count to 4 times the number of transfers Operation is not guaranteed i...

Page 494: ...ation address Initial value 1 Destination address is incremented 1 for byte transfer size 2 for word transfer size 4 for longword transfer size 16 for 16 byte transfer size 1 0 Destination address is decremented 1 for byte transfer size 2 for word transfer size 4 for longword transfer size 16 for 16 byte transfer size 1 Reserved setting prohibited Bits 13 and 12 Source Address Mode Bits 1 0 SM1 SM...

Page 495: ... for the dual address mode Bit 9 Auto Request Mode Bit AR Selects either auto request mode in which transfer requests are generated automatically within the DMAC or a mode using external requests or requests from on chip peripheral modules SCIF TPU SIOF SIO The AR bit is initialized to 0 by a reset and in standby mode Its value is retained during a module standby Bit 9 AR Description 0 External on...

Page 496: ...ained during a module standby Bit 6 DS Description 0 Detected by level Initial value Can be set only in cycle steal mode 1 Detected by edge Bit 5 DREQn Level Bit DL Selects the DREQn input detection level The DL bit is initialized to 0 by a reset and in standby mode Its value is retained during a module standby Bit 5 DL Description 0 When DS is 0 DREQ is detected by low level when DS is 1 DREQ is ...

Page 497: ...y Bit 2 IE Description 0 Interrupt request disabled Initial value 1 Interrupt request enabled Bit 1 Transfer End Flag Bit TE Indicates that the transfer has ended When the value in the DMA transfer count register TCR becomes 0 the DMA transfer ends normally and the TE bit is set to 1 When TCR is not 0 the TE bit is not set if the transfer ends because of an NMI interrupt or DMA address error or be...

Page 498: ...ed 11 2 5 DMA Vector Number Registers 0 and 1 VCRDMA0 VCRDMA1 Bit 31 30 29 11 10 9 8 Initial value 0 0 0 0 0 0 0 R W R R R R R R R Bit 7 6 5 4 3 2 1 0 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 Initial value R W R W R W R W R W R W R W R W R W DMA vector number registers 0 and 1 VCRDMA0 VCRDMA1 are 32 bit read write registers that set the DMAC transfer end interrupt vector number Only the lower eight bits of...

Page 499: ...ad as 0 The write value should always be 0 Bits 4 to 0 Resource Select Bits 4 to 0 RS4 RS0 Specify which transfer request to input to the DMAC Changing the transfer request source must be done when the DMA enable bit DE is 0 See section 11 3 4 DMA Transfer Types for the possible setting combinations Bits RS4 to RS0 are initialized to 001 by a reset Bit 4 RS4 Bit 3 RS3 Bit 2 RS2 Bit 1 RS1 Bit 0 RS0...

Page 500: ...terrupt request 1 0 0 0 0 Reserved setting prohibited 1 SIOF RDFI SIO with FIFO receive data full interrupt request 1 0 SIOF TDEI SIO with FIFO transmit data empty interrupt request 1 Reserved setting prohibited 1 0 0 Reserved setting prohibited 1 SIO channel 1 RDFI SIO channel 1 receive data full interrupt request 1 0 SIO channel 1 TDEI SIO channel 1 transmit data empty interrupt request 1 Reserv...

Page 501: ... bit value including the upper 28 bits DMAOR is initialized to H 00000000 by a reset and in standby mode It retains its value when the module standby function is used Bits 31 to 4 Reserved These bits are always read as 0 The write value should always be 0 Bit 3 Priority Mode Bit PR Specifies whether a fixed channel priority order or round robin mode is to be used there are simultaneous transfer re...

Page 502: ...control register CHCR and the DME bit are set to 1 To clear the NMIF bit read 1 from it and then write 0 Operation is completed up to the end of the DMAC transfer being executed when NMI was input When the NMI interrupt is input while the DMAC is not operating the NMIF bit is set to 1 The NMIF bit is initialized to 0 by a reset or in the standby mode It retains its value when the module standby fu...

Page 503: ...er DMAOR are initialized initializing sets each register so that ultimately the condition DE 1 DME 1 TE 0 NMIF 0 AE 0 is satisfied the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 NMIF 0 AE 0 2 When a transfer request occurs and transfer is enabled the DMAC transfers 1 transfer unit of data In auto request mode the transfer begins ...

Page 504: ...s No Yes No 3 5 4 2 Start End normally End transfer Yes 16 byte transfer in progress NMIF 1 or AE 1 or DE 0 or DME 0 NMIF 1 or AE 1 or DE 0 or DME 0 Bus mode transfer request mode DREQ detec tion method Notes 1 In auto request mode the transfer will start when the NMIF AE and TE bits are all 0 and the DE and DME bits are then set to 1 2 Cycle steal mode 3 In burst mode DREQ edge detection external...

Page 505: ...ng the AR and RS Bits CHCR DRCR AR RS4 RS3 RS2 RS1 RS0 Request Mode Resource Selection 0 0 0 0 0 0 Module request mode DREQ external request 1 0 1 SCIF channel 1 RXI 1 0 SCIF channel 1 TXI 1 0 0 1 SCIF channel 2 RXI 1 0 SCIF channel 2 TXI 1 0 TPU TGI0A 1 TPU TGI0B 1 0 TPU TGI0C 1 TPU TGI0D 1 0 0 0 SIOF RDFI 1 0 SIOF TDEI 1 0 1 SIO channel 1 RDFI 1 0 SIO channel 1 TDEI 1 0 0 1 SIO channel 2 RDFI 1 ...

Page 506: ...ce with DACK 1 Single address mode Data transferred from device to memory External device with DACK External memory or memory mapped external device Note External memory memory mapped external device and on chip peripheral module excluding DMAC BSC UBC cache memory E DMAC and EtherC Choose to detect DREQn either by the falling edge or by level using the DS and DL bits in CHCR0 and CHCR1 DS 0 is le...

Page 507: ...TXI TDEI and TPU general registers table 11 6 If DMA transfer is enabled DE 1 DME 1 TE 0 NMIF 0 AE 0 DMA transfer starts upon input of a transfer request signal When RXI or RDFI transfer request due to an SCIF SIOF or SIO receive data full condition is set as a transfer request the transfer source must be the receive data register of the corresponding module SCFRDR or SIRDR When TXI or TDEI transf...

Page 508: ...TPU channel 0A TGI0A Any excluding on chip RAM Any excluding on chip RAM Cycle steal Edge active low 1 TPU channel 0B TGI0B Any excluding on chip RAM Any excluding on chip RAM Cycle steal Edge active low 1 0 TPU channel 0C TGI0C Any excluding on chip RAM Any excluding on chip RAM Cycle steal Edge active low 1 TPU channel 0D TGI0D Any excluding on chip RAM Any excluding on chip RAM Cycle steal Edge...

Page 509: ... Priorities When the DMAC receives simultaneous transfer requests on two channels it selects a channel according to a predetermined priority order There is a choice of two priority modes fixed or round robin The mode is selected by the priority bit PR in the DMA operation register DMAOR Fixed Priority Mode In this mode the relative channel priority levels are fixed When PR is set to 0 channel 0 ha...

Page 510: ... reset channel 1 has higher priority than channel 0 Figure 11 5 shows how the priority changes when channel 0 and channel 1 transfers are requested simultaneously and another channel 0 transfer is requested after the first two transfers end The DMAC operates as follows 1 Transfer requests are generated simultaneously to channels 1 and 0 2 Channel 1 has the higher priority so the channel 1 transfer...

Page 511: ...Channel 1 transfer starts 3 Channel 1 transfer ends 5 Channel 0 transfer ends 7 Channel 0 transfer starts 4 Channel 0 transfer starts 8 Channel 0 transfer ends Priority changes 1 0 0 1 1 0 1 0 Transfer requests Waiting channel DMAC operation Channel priority order Priority changes Priority does not change Waiting for transfer request Figure 11 5 Channel Priority in Round Robin Mode ...

Page 512: ...ual Dual Dual Dual On chip peripheral module Not available Dual Dual Dual Dual On chip memory Not available Dual Dual Dual Dual Single Single address mode Dual Dual address mode Note Access size permitted by peripheral module register used as transfer source or transfer destination excluding DMAC BSC UBC cache memory E DMAC and EtherC Address Modes Single Address Mode In single address mode both t...

Page 513: ...s of transfers are possible in single address mode 1 transfers between external devices with DACK and memory mapped external devices and 2 transfers between external devices with DACK and external memory For both of them transfer must be requested by the external request signal DREQn For the combination of the specifiable setting to perform data transfer using an external request DREQn see table 1...

Page 514: ...memory space Data output from external device with DACK DACK signal active low to external device with DACK a External device with DACK to external memory space Address output to external memory space Data output from external memory space Read strobe signal to external memory space DACK signal active low to external device with DACK b External memory space to external device with DACK Figure 11 7...

Page 515: ... External data bus Data flow 1 Read cycle 2 Write cycle Figure 11 8 Data Flow in Dual Address Mode In dual address mode transfers external memory and memory mapped external devices can be mixed without restriction Specifically this enables transfers between the following Transfer between external memory and external memory Transfer between external memory and memory mapped external device Transfer...

Page 516: ...tively must be the transfer destination or transfer source see table 11 6 For the combination of the specifiable setting to perform data transfer using an external request DREQn see table 11 9 Dual address mode outputs DACKn in either the read cycle or write cycle The acknowledge transfer mode bit AM of the DMA channel control registers 0 and 1 CHCR0 and 1 specifies whether DACK is output in eithe...

Page 517: ...ies of transfer destination transfer source and transfer request source with the exception of transfers between on chip peripheral modules The CPU may take the bus twice when an acknowledge signal is output during the write cycle or in single address mode Figure 11 10 shows an example of DMA transfer timing in cycle steal mode The transfer conditions for the example in the figure are as shown belo...

Page 518: ...ule however cycle steal mode is always used Figure 11 11 shows an example of DMA transfer timing in burst mode The transfer conditions for the example in the figure are as shown below CPU CPU CPU DMAC DMAC DMAC DMAC CPU DREQn Single address mode DREQn level detection Bus cycle CPU CPU Figure 11 11 DMA Transfer Timing in Burst Mode Single Address DREQn Falling Edge Detection Refreshes cannot be per...

Page 519: ...xternal B C 1 2 4 16 8 Automatic B C 1 2 4 16 Internal peripheral module 1 C 1 2 4 Between external memory and memory External B C 1 2 4 16 8 mapped external device Automatic B C 1 2 4 16 Internal peripheral module 1 C 1 2 4 Between memory mapped external devices External B C 1 2 4 16 8 Automatic B C 1 2 4 16 Internal peripheral module 1 C 1 2 4 Between external memory and internal External B C 1 ...

Page 520: ...it and the DL bit of CHCR0 and CHCR1 to 1 and 0 respectively detection at the falling edge of DREQn In addition the bus mode can only be set to cycle steal mode 4 Specify the access size that is allowed by the internal peripheral module registers which are a transfer source or a transfer destination 5 When transferring data from internal memory to a memory mapped external device set DACKn to write...

Page 521: ...ing in burst mode and there is a transfer request to a channel 0 with a higher priority the transfer of the channel with higher priority 0 will begin immediately When channel 0 is also operating in the burst mode the channel 1 transfer will continue as soon as the channel 0 transfer has completely finished When channel 0 is in cycle steal mode channel 1 will begin operating again after channel 0 c...

Page 522: ...ut begins and becomes invalid 0 5 cycles before the address output ends See figure 11 13 The output timing of the acknowledge signal varies with the settings of the connected memory space The output timing of acknowledge signals in the memory spaces is shown in figure 11 13 Clock DACKn Active high Address bus CPU DMAC 0 5 cycles Figure 11 13 Example of DACKn Output Timing Acknowledge Signal Output...

Page 523: ... DACKn Output in Ordinary Space Accesses AM 1 In a longword access of a 16 bit external device figure 11 16 or an 8 bit external device figure 11 17 or a word access of an 8 bit external device figure 11 18 the lower and upper addresses are output 2 and 4 times in each DMAC access in order to align the data For all of these addresses the acknowledge signal becomes valid simultaneous with the start...

Page 524: ...Ordinary Space Accesses AM 0 Longword Access to 16 Bit External Device Clock DACKn Active high Address bus CPU DMAC read HH DMAC read HL DMAC read LH DMAC read LL Basic timing Figure 11 17 DACKn Output in Ordinary Space Accesses AM 0 Longword Access to 8 Bit External Device Clock DACKn Active high Address bus CPU DMAC read H DMAC read L Invalid write DMAC write Basic timing Figure 11 18 DACKn Outp...

Page 525: ...g figure 11 20 At this time the acknowledge signal is extended until the write address is output after the invalid read A synchronous DRAM burst read is performed in the case of 16 byte transfer As 16 byte transfer is enabled only in auto request mode and in external request mode with edge detection when using on chip peripheral module requests or external request mode with level detection byte wo...

Page 526: ...id read DMAC read basic timing DMAC write basic timing Row address Column address Row address Read Read command Figure 11 20 DACKn Output in Synchronous DRAM Single Read Auto Precharge AM 0 Clock DACKn Active high Address bus DMAC write basic timing Column address Row address Figure 11 21 DACKn Output in Synchronous DRAM Write Auto Precharge AM 1 ...

Page 527: ...fferent from the previous address the acknowledge signal is output across the precharge row address read command wait and read address figure 11 23 Clock DACKn Active high Address bus CPU DMAC read basic timing Read command Read 1 Read 2 Read 3 Read 4 Figure 11 22 DACKn Output in Synchronous DRAM Burst Read Bank Active Same Row Address AM 0 Clock DACKn Active high Address bus CPU DMAC read basic t...

Page 528: ...RAM read has only burst mode during a single read an invalid address is output the acknowledge signal is output on the same timing At this time the acknowledge signal is extended until the write address is output after the invalid read Clock DACKn Active high Address bus CPU Read Invalid read DMAC read basic timing DMAC write basic timing Read command Row address Column address Figure 11 24 DACKn ...

Page 529: ...11 26 When the row address is different from the previous address the acknowledge signal is output across the precharge row address wait and column address figure 11 27 Clock DACKn Active high Address bus DMAC write basic timing Column address Figure 11 26 DACKn Output in Synchronous DRAM Write Bank Active Same Row Address AM 1 Clock DACKn Active high Address bus DMAC write basic timing Precharge ...

Page 530: ...gle mode Bus cycle Basic bus cycle Notes 1 Do not set a 16 byte unit operation is not guaranteed if this setting is made 2 Cycle steal mode must be set when DREQ is level detected Clock Bus cycle DREQn Active high DMAC1 DMAC2 DMAC3 DACK1 DACK3 DACK2 1st acceptance CPU CPU CPU CPU CPU DACKn Active high CAS RD WR WEn DQMxx RAS Blind zone 2nd acceptance 3rd acceptance 4th acceptance Figure 11 28 a Sy...

Page 531: ... Figure 11 28 b Synchronous DRAM One Cycle Write Timing Acknowledge Signal Output when External Memory Is Set as DRAM When external memory is set as DRAM and a row address is output during a read or write the acknowledge signal is output across the row address and column address figures 11 29 11 31 Clock DACKn Active high Address bus DMAC read or write basic timing Precharge Row address Column add...

Page 532: ...gh Address bus DMAC read or write basic timing Column address Figure 11 30 DACKn Output in DRAM Burst Accesses Same Row Address AM 0 or 1 Clock DACKn Active high Address bus DMAC read or write basic timing Pre charge Row address Column address Figure 11 31 DACKn Output in DRAM Burst Accesses Different Row Address AM 0 or 1 ...

Page 533: ...ted the timing of the next input detection varies with the bus mode address mode DREQn input detection and the memory connected DREQn Pin Input Detection Timing in Cycle Steal Mode In cycle steal mode once a request is detected from the DREQn pin the request signal is not detected until DACKn signal output in the next external bus cycle In cycle steal mode request detection is performed from DACKn...

Page 534: ... acceptance CPU CPU CPU CPU DACKn Active high Bus cycle DREQn Rising edge detection Figure 11 33 DREQn DACKn Handshaking Transfer Width Byte Word Longword DREQn Detection Method Edge Detection Transfer bus mode Cycle steal mode DACKn output timing Read DACK write DACK Transfer address mode Dual single mode Bus cycle Basic bus cycle Clock Bus cycle DREQn Active high DACKn Active high Requests accep...

Page 535: ...n Active high DREQn Active high 1st acceptance Blind zone Figure 11 35 When a16 Bit External Device is Connected Edge Detection Clock Bus cycle CPU DMAC HH DACK HH DACK HL DACK LH DACK LL DMAC HL DMAC LH DMAC LL 1st acceptance 2nd acceptance CPU Blind zone Blind zone DACKn Active high DREQn Active high Figure 11 36 When an 8 Bit External Device is Connected Edge Detection ...

Page 536: ...single mode Bus cycle Basic bus cycle Clock Bus cycle CPU CPU DMAC 1 DMAC 2 DMAC 3 DMAC 4 DMA 1st acceptance 2nd acceptance DACK 1 DACK 2 DACK 3 DACK 4 Blind zone Note n is the nth 16 byte transfer DACKn Active high DREQn Active high Figure 11 37 DREQn Pin Input Detection Timing in Cycle Steal Mode with Edge Detection 16 Byte Transfer Setting Cycle Steal Mode Level Detection In level detection mod...

Page 537: ...nd zone 2nd acceptance DACKn Active high DREQn Active high Figure 11 38 DREQn Pin Input Detection Timing in Cycle Steal Mode with Level Detection Byte Word Longword Setting Clock Bus cycle DMAC H DACK H DACK L 1st acceptance CPU Blind zone Blind zone 2nd acceptance DMAC L CPU DACKn Active high DREQn Active high Figure 11 39 When a 16 Bit External Device is Connected Level Detection ...

Page 538: ...ction is valid for DREQn input Operation is not guaranteed if level detection is set With edge detection of DREQn input once a request is detected DMA transfer continues until the transfer end condition is satisfied regardless of the state of the DREQn pin Request detection is not performed during this time When the transfer start conditions are fulfilled after the end of transfer request detectio...

Page 539: ...sfer Transfer end when DE 0 in CHCR When the DMA enable bit DE in CHCR is cleared DMA transfers in the affected channel are halted The TE bit is not set when this happens Conditions for Both Channels Ending Simultaneously Transfers on both channels end when either of the following conditions is met The NMIF NMI flag bit or AE address error flag bit in DMAOR is set to 1 The DMA master enable DME bi...

Page 540: ...ernal Grew logic increases if address comparisons are required and there is also the possibility that delays may interfere with timing requirements The specifications for BH have therefore been updated in order to solve these problems Now if burst transfer is possible using the present address this information is passed to the external Grew logic This provides enhanced support for PCI bus connecti...

Page 541: ... 0 3 TA 18 0 2 IE 17 0 1 TE 16 0 0 DE 1 16 byte unit four long words transferred Source address is incremented Destination address is incremented Don t care DMA transfer allowed Figure 11 42 Register Settings When Using BH BH BH BH Summary of BH BH BH BH Timing Figure 11 43 is a summary of the BH output timing CPU DMAC read 0 DMAC read 1 DMAC read 2 DMAC read 3 DMAC write 0 DMAC write 1 DMAC write...

Page 542: ...nsfers 64 TCR1 H 0040 Transfer destination address Increment CHCR1 H 4045 Transfer source address Fixed Bus mode Cycle steal Transfer unit Byte DEI interrupt request at end of transfer DE 1 Channel priority Fixed 0 1 DME 1 DMAOR H 0001 Transfer request source transfer request signal SCIF RXI DRCR1 H 05 Note Make sure the SCIF settings have interrupts enabled and the appropriate CPU interrupt level...

Page 543: ...m the peripheral module by the DMA transfer is not completed before the next transfer request signal from that module subsequent DMA transfers may not be possible 11 The following restrictions apply when using dual address mode for 16 byte transfer in cycle steal mode a When external request and level detection are set do not input DREQn during cycles in which DACKn is not active after the start o...

Page 544: ...ess mode or built in peripheral module request set the priority mode to priority order fixed mode 13 When SDRAM is connected set the upper limit of external bus frequency in DMA single address mode transfers to 31 25 MHz 14 In the dual address mode bits TS1 and TS0 transfer size in CHCR0 and CHCR1 should be cleared to 00 byte unit setting if a destination address as been set in internal memory ...

Page 545: ...cycle of external clocks 12 1 1 Features The FRT has the following features Choice of four counter input clocks The counter input clock can be selected from three internal clocks Pφ 8 Pφ 32 Pφ 128 and an external clock enabling external event counting Two independent comparators Two waveform outputs can be generated Input capture Choice of rising edge or falling edge Counter clear specification Th...

Page 546: ...Clock select Clock Compare match A Overflow Clear Compare match B Capture OCRA H L Comparator A FRC H L Comparator B OCRB H L FICR H L FTCSR TIER TCR TOCR Bus interface OCRA B FRC FICR FTCSR TIER TCR TOCR Output compare registers A B 16 bits Free running counter 16 bits Input capture register 16 bits Free running timer control status register 8 bits Timer interrupt enable register 8 bits Timer con...

Page 547: ...W H 01 HFFFFFE10 Free running timer control status register FTCSR R W 1 H 00 HFFFFFE11 Free running counter H FRC H R W H 00 HFFFFFE12 Free running counter L FRC L R W H 00 HFFFFFE13 Output compare register A H OCRA H R W H FF HFFFFFE14 2 Output compare register A L OCRA L R W H FF HFFFFFE15 2 Output compare register B H OCRB H R W H FF HFFFFFE14 2 Output compare register B L OCRB L R W H FF HFFFF...

Page 548: ...detailed information FRC is initialized to H 0000 by a reset in standby mode and when the module standby function is used 12 2 2 Output Compare Registers A and B OCRA and OCRB Bit 15 14 13 3 2 1 0 Initial value 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W OCR is composed of two 16 bit read write registers OCRA and OCRB The contents of OCR are always compared to the FRC value When the two values a...

Page 549: ...P See Section 12 3 CPU Interface for more detailed information To ensure that the input capture operation is reliably performed set the pulse width of the input capture input signal to six system clocks φ or more FICR is initialized to H 0000 by a reset in standby mode and when the module standby function is used 12 2 4 Timer Interrupt Enable Register TIER Bit 7 6 5 4 3 2 1 0 ICIE OCIAE OCIBE OVIE...

Page 550: ...bled Initial value 1 Interrupt request OCIB caused by OCFB enabled Bit 1 Timer Overflow Interrupt Enable OVIE Selects enabling disabling of the OVI interrupt request when the overflow flag OVF in FTCSR is set to 1 Bit 1 OVIE Description 0 Interrupt request OVI caused by OVF disabled initial value 1 Interrupt request OVI caused by OVF enabled Bit 0 Reserved This bit is always read as 1 The write va...

Page 551: ...rite value should always be 0 Bit 3 Output Compare Flag A OCFA Status flag that indicates when the values of the FRC and OCRA match This flag is cleared by software and set by hardware It cannot be set by software Bit 3 OCFA Description 0 Clearing condition When OCFA is read while set to 1 and then 0 is written to it Initial value 1 Setting condition When the FRC value becomes equal to OCRA Bit 2 ...

Page 552: ...atch of FRC and OCRA Bit 0 CCLRA Description 0 FRC clear disabled Initial value 1 FRC cleared on compare match A 12 2 6 Timer Control Register TCR Bit 7 6 5 4 3 2 1 0 IEDG CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R R R R R R W R W TCR is an 8 bit read write register that selects the input edge for input capture and selects the input clock for FRC TCR is initialized to H 00 by a reset in sta...

Page 553: ... controls switching between access of output compare registers A and B TOCR is initialized to H E0 by a reset in standby mode and when the module standby function is used Bits 7 to 5 Reserved These bits are always read as 1 The write value should always be 1 Bit 4 Output Compare Register Select OCRS OCRA and OCRB share the same address The OCRS bit controls which register is selected when reading ...

Page 554: ...ch results in the upper byte of data being stored in TEMP The lower byte is then written which results in 16 bits of data being written to the register when combined with the upper byte value in TEMP Reading from 16 bit Registers The upper byte of data is read which results in the upper byte value being transferred to the CPU The lower byte value is transferred to TEMP The lower byte is then read ...

Page 555: ...EJ09B0292 0200 CPU H AA upper byte Data bus within module Bus interface TEMP H AA FRC H FRC L Write to upper byte CPU H 55 lower byte Data bus within module Bus interface TEMP H AA FRC H H AA FRC L H 55 Write to lower byte Figure 12 2 FRC Access Operation CPU Writes H AA55 to FRC ...

Page 556: ...J09B0292 0200 CPU H AA upper byte TEMP H 55 FRC H H AA FRC L H 55 Data bus within module Bus interface Read from upper byte CPU H 55 lower byte TEMP H AA FRC H FRC L Data bus within module Bus interface Read from lower byte Figure 12 3 FRC Access Operation CPU Reads H AA55 from FRC ...

Page 557: ...8 is used Figure 12 4 shows the timing Pφ N 1 N N 1 Internal clock FRC input clock FRC Figure 12 4 Count Timing Internal Clock Operation External Clock Operation Set the CKS1 and CKS0 bits in TCR to select the external clock External clock pulses are counted on the rising edge The pulse width of the external clock must be at least 6 system clocks φ A smaller pulse width will result in inaccurate o...

Page 558: ...utput pins FTOA FTOB Figure 12 6 shows the timing for output of output compare A Clear N N N N N 1 N 1 Pφ FRC OCRA Compare match A signal OLVLA Output compare A output pin FTOA Note Indicates instruction execution by software Figure 12 6 Output Timing for Output Compare A 12 4 3 FRC Clear Timing FRC can be cleared on compare match A Figure 12 7 shows the timing Pφ Compare match A signal FRC N H 00...

Page 559: ...he timing when the rising edge is selected IEDG 1 Pφ Input capture input pin Input capture signal Figure 12 8 Input Capture Signal Timing Normal When the input capture signal is input when FICR is read upper byte read the input capture signal is delayed by one cycle of Pφ Figure 12 9 shows the timing Pφ Input capture input pin Input capture signal FICR upper byte read cycle Figure 12 9 Input Captu...

Page 560: ... FICR N N Figure 12 10 ICF Setting Timing 12 4 6 Output Compare Flag OCFA OCFB Setting Timing The compare match signal output when OCRA or OCRB matches the FRC value sets output compare flag OCFA or OCFB to 1 The compare match signal is generated in the last state in which the values matched at the timing for updating the count value that matched the FRC After OCRA or OCRB matches the FRC no compa...

Page 561: ...OCRA OCRB Compare match signal OCFA OCFB N 1 N N Figure 12 11 OCF Setting Timing 12 4 7 Timer Overflow Flag OVF Setting Timing FRC overflow from H FFFF to H 0000 sets the timer overflow flag OVF to 1 Figure 12 12 shows the timing Pφ FRC Overflow signal OVF H 0000 H FFFF Figure 12 12 OVF Setting Timing ...

Page 562: ...ontroller INTC for more information about priorities and the relationship to interrupts other than those of the FRT Table 12 3 FRT Interrupt Sources and Priorities Interrupt Source Description Priority ICI Interrupt by ICF High OCIA OCIB Interrupt by OCFA or OCFB OVI Interrupt by OVF Low 12 6 Example of FRT Use Figure 12 13 shows an example in which pulses with a 50 duty factor and arbitrary phase...

Page 563: ... 7 1 Contention between FRC Write and Clear When a counter clear signal is generated with the timing shown in figure 12 14 during the write cycle for the lower byte of FRC writing does not occur to the FRC and the FRC clear takes priority Pφ FRC lower byte write cycle Address Internal write signal Counter clear signal FRC FRC address N H 0000 Figure 12 14 Contention between FRC Write and Clear ...

Page 564: ...ent When an increment occurs with the timing shown in figure 12 15 during the write cycle for the lower byte of FRC no increment is performed and the counter write takes priority FRC FRC address N M Write data Pφ FRC lower byte write cycle Address Internal write signal FRC input clock Figure 12 15 Contention between FRC Write and Increment ...

Page 565: ... match occurs with the timing shown in figure 12 16 during the write cycle for the lower byte of OCRA or OCRB the OCR write takes priority and the compare match signal is disabled FRC Compare match signal OCR OCR address N M N N 1 Write data Disabled Pφ FRC lower byte write cycle Address Internal write signal Figure 12 16 Contention between OCR and Compare Match ...

Page 566: ...d by dividing the system clock φ is detected When a clock is switched to high before the switching and to low after switching as shown in case 3 in table 12 4 the switchover is considered a falling edge and an FRC clock pulse is generated causing FRC to increment FRC may also increment when switching between an internal clock and an external clock Table 12 4 Internal Clock Switching and FRC Operat...

Page 567: ...C clock FRC Rewrite of CKS bit 4 High to high switch N N 1 N 2 Clock before switching Clock after switching FRC clock FRC Rewrite of CKS bit Note Because the switchover is considered a falling edge FRC starts counting up 12 7 5 Timer Output FTOA FTOB During a power on reset the timer outputs FTOA FTOB will be unreliable until the oscillation stabilizes The initial value is output after the oscilla...

Page 568: ...Section 12 16 Bit Free Running Timer FRT Rev 2 00 Mar 09 2006 page 542 of 906 REJ09B0292 0200 ...

Page 569: ...n an interval timer interrupt is generated at each counter overflow The WDT is also used when recovering from standby mode in modifying a clock frequency and in clock pause mode 13 1 1 Features The WDT includes the following features Can be switched between watchdog timer mode and interval timer mode WDTOVF output in watchdog timer mode The WDTOVF signal is output externally when the counter overf...

Page 570: ...ernal reset signal WDT φ See figure 3 1 Block Diagram of Clock Pulse Generator Circuit WTCSR Watchdog timer control status register WTCNT Watchdog timer counter RSTCSR Reset control status register Note The internal reset signal can be generated by a register setting The type of reset can be selected power on or manual reset Figure 13 1 WDT Block Diagram 13 1 3 Pin Configuration Table 13 1 shows t...

Page 571: ...13 2 Register Descriptions 13 2 1 Watchdog Timer Counter WTCNT Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W WTCNT is an 8 bit read write register The method of writing to WTCNT differs from that of most other registers to prevent inadvertent rewriting See section 13 2 4 Notes on Register Access for details When the timer enable bit TME in the watchdog timer...

Page 572: ... are not initialized in standby mode when the clock frequency is changed or in clock pause mode Bit 7 Overflow Flag OVF Indicates that WTCNT has overflowed from H FF to H 00 in interval timer mode It is not set in watchdog timer mode Bit 7 OVF Description 0 No overflow of WTCNT in interval timer mode Initial value Cleared by reading OVF then writing 0 in OVF 1 WTCNT overflow in interval timer mode...

Page 573: ...y dividing the frequency of the system clock φ Description Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Clock Source Overflow Interval φ φ φ φ 60 MHz 0 0 0 φ 4 Initial value 17 0 µs 1 φ 128 544 µs 1 0 φ 256 1 1 ms 1 φ 512 2 2 ms 1 0 0 φ 1024 4 4 ms 1 φ 2048 8 7 ms 1 0 φ 8192 34 8 ms 1 φ 16384 69 6 ms Note The overflow interval listed is the time from when the WTCNT begins counting at H 00 until an overflow oc...

Page 574: ...et in interval timer mode Bit 7 WOVF Description 0 No WTCNT overflow in watchdog timer mode Initial value Cleared by reading WOVF then writing 0 in WOVF 1 Set by WTCNT overflow in watchdog timer mode Bit 6 Reset Enable RSTE Selects whether to reset the chip internally if WTCNT overflows in watchdog timer mode Bit 6 RSTE Description 0 Not reset when WTCNT overflows Initial value LSI not reset inter...

Page 575: ...te data from the lower byte to WTCNT or WTCSR Writing to WTCNT 15 8 7 0 Address H FFFFFE80 H 5A Write data Writing to WTCSR 15 8 7 0 Address H FFFFFE80 H A5 Write data Figure 13 2 Writing to WTCNT and WTCSR Writing to RSTCSR RSTCSR must be written by a word access to address H FFFFFE82 It cannot be written by byte or longword transfer instructions Procedures for writing 0 in WOVF bit 7 and for wri...

Page 576: ...by rewriting the WTCNT value normally by writing H 00 before overflow occurs Thus WTCNT will not overflow while the system is operating normally but if WTCNT fails to be rewritten and overflows occur due to a system crash or the like a WDTOVF signal is output figure 13 4 The WDTOVF signal can be used to reset the system The WDTOVF signal is output for 512 φ clock cycles If the RSTE bit in RSTCSR i...

Page 577: ... TME 1 H 00 written in WTCNT H 00 written in WTCNT WDTOVF and internal reset generated H FF H 00 512 φ clocks 2048 φ clocks WDTOVF signal Internal reset signal Time WT IT Timer mode select bit TME Timer enable bit Note Internal reset signal is generated only when the RSTE bit is set to 1 Figure 13 4 Operation in Watchdog Timer Mode ...

Page 578: ...When using standby mode set the WDT as described below Transition to Standby Mode The TME bit in WTCSR must be cleared to 0 to stop the watchdog timer counter before it enters standby mode The chip cannot enter standby mode while the TME bit is set to 1 Set bits CKS2 to CKS0 in WTCSR so that the counter overflow interval is equal to or longer than the oscillation settling time See section 22 Elect...

Page 579: ...igure 13 6 WTCNT H FF H 00 Overflow signal internal signal OVF Figure 13 6 Timing of OVF Setting 13 3 5 Timing of Watchdog Timer Overflow Flag WOVF Setting When WTCNT overflows the WOVF flag in RSTCSR is set to 1 and a WDTOVF signal is output When the RSTE bit is set to 1 WTCNT overflow enables an internal reset signal to be generated for the entire chip figure 13 7 WTCNT H FF H 00 Overflow signal...

Page 580: ... Contention between WTCNT Write and Increment 13 4 2 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 are altered while the WDT is running the count may increment incorrectly Always stop the watchdog timer by clearing the TME bit to 0 before changing the values of bits CKS2 to CKS0 13 4 3 Switching between Watchdog Timer Mode and Interval Timer Mode The WDT may not operate corre...

Page 581: ...wn in figure 13 9 Reset input Reset signal to entire system Chip RES WDTOVF Figure 13 9 Example of Circuit for System Reset with WDTOVF WDTOVF WDTOVF WDTOVF Signal 13 4 5 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode the chip will not reset internally when a WTCNT overflow occurs but WTCNT and WTCSR in the WDT will reset When using sleep mode do not u...

Page 582: ...Section 13 Watchdog Timer WDT Rev 2 00 Mar 09 2006 page 556 of 906 REJ09B0292 0200 ...

Page 583: ...eception enabling fast efficient and continuous communication 14 1 1 Features The SCIF has the following features Choice of synchronous or asynchronous serial communication mode Asynchronous mode Serial data communication is executed using an asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous commu...

Page 584: ...cture enabling continuous serial data transmission and reception However IrDA communication is carried out in half duplex mode Built in baud rate generator allows a choice of bit rates Choice of transmit receive clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt sources There are four interrupt sources transmit FIFO data empty break receive FIFO data...

Page 585: ...mission reception control Baud rate generator Clock External clock Pφ Pφ 4 Pφ 16 Pφ 64 BRI IrDA SCI switchover to IrDA block TxI RxI ERI SCIF Legend SCRSR Receive shift register SCFRDR Receive FIFO data register SCTSR Transmit shift register SCFTDR Transmit FIFO data register SCSMR Serial mode register SCSCR Serial control register Bus interface Internal data bus SC1SSR Serial status 1 register SC...

Page 586: ...he serial pins shown in table 14 1 Table 14 1 SCIF Pins Channel Name Abbreviation I O Function 1 Serial clock pin SCK1 Input output Clock input output Receive data pin RxD1 Input Receive data input Transmit data pin TxD1 Output Transmit data output Transmit request pin RTS Output Transmit request Transmit enable pin CTS Input Transmit enable 2 Serial clock pin SCK2 Input output Clock input output ...

Page 587: ...ve FIFO data register SCFRDR1 R Undefined H FFFFFCCC 8 FIFO control register SCFCR1 R W H 00 H FFFFFCCE 8 FIFO data count register SCFDR1 R H 0000 H FFFFFCD0 16 FIFO error register SCFER1 R H 0000 H FFFFFCD2 16 IrDA mode register SCIFMR1 R W H 00 H FFFFFCD4 8 2 Serial mode register SCSMR2 R W H 00 H FFFFFCE0 8 Bit rate register SCBRR2 R W H FF H FFFFFCE2 8 Serial control register SCSCR2 R W H 00 H...

Page 588: ... to the receive FIFO data register SCFRDR automatically SCRSR cannot be read or written to directly 14 2 2 Receive FIFO Data Register SCFRDR Bit 7 6 5 4 3 2 1 0 R W R R R R R R R R The receive FIFO data register SCFRDR is a 16 stage FIFO register 8 bits per stage that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR to SCFRDR ...

Page 589: ...rom SCFTDR to SCTSR and transmission started automatically SCTSR cannot be read or written to directly 14 2 4 Transmit FIFO Data Register SCFTDR Bit 7 6 5 4 3 2 1 0 R W W W W W W W W W The transmit FIFO data register SCFTDR is a 16 stage FIFO register 8 bits per stage that stores data for serial transmission When the SCIF detects that SCTSR is empty it transfers the transmit data written in SCFTDR...

Page 590: ...andby mode Bit 7 Communication Mode C A Selects asynchronous mode or synchronous mode as the SCIF operating mode In IrDA communication mode this bit must be cleared to 0 Bit 7 C A A A A Description 0 Asynchronous mode Initial value 1 Synchronous mode Bit 6 Character Length CHR IrDA Clock Select 3 ICK3 Selects 7 or 8 bits as the data length in asynchronous mode In synchronous mode a fixed data leng...

Page 591: ...CK1 Selects either even or odd parity for use in parity addition and checking The O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking in asynchronous mode The O E bit setting is invalid in synchronous mode and when parity addition and checking is disabled in asynchronous mode Bit 4 O E E E E Description 0 Even parity 1 Initial value 1 Odd parity 2 No...

Page 592: ... if it is 0 it is treated as the start bit of the next transmit character In IrDA communication mode bit 3 is the IrDA clock select 0 ICK0 bit enabling appropriate clock pulses to be generated according to its setting See Pulse Width Selection in section 14 3 6 Operation in IrDA Mode for details Bit 2 Multiprocessor Mode MP Selects a multiprocessor format When a multiprocessor format is selected t...

Page 593: ...n to by the CPU at all times SCSCR is initialized to H 00 by a reset by the module standby function and in standby mode Bit 7 Transmit Interrupt Enable TIE Enables or disables transmit FIFO data empty interrupt TXI request generation when after serial transmit data is transferred from the transmit FIFO data register SCFTDR to the transmit shift register SCTSR the number of data bytes in SCFTDR fal...

Page 594: ...bit to 0 With the RDF flag read receive data from SCFRDR until the number of receive data bytes is less than the receive trigger set number then read 1 from the RDF flag and clear it to 0 Bit 5 Transmit Enable TE Enables or disables the start of serial transmission by the SCIF Bit 5 TE Description 0 Transmission disabled 1 Initial value 1 Transmission enabled 2 Notes 1 The TDRE flag in SC1SSR is f...

Page 595: ...n SC1SSR and ORER flags in SC2SSR is not performed When receive data with MPB 1 is received the MPB flag in SC2SSR is set to 1 the MPIE bit is cleared to 0 automatically and generation of RXI and ERI when the RIE bit in SCSCR is set to 1 and FER and ORER flag setting is enabled Bit 2 Reserved This bit is always read as 0 The write value should always be 0 Bits 1 and 0 Clock Enable 1 and 0 CKE1 CKE...

Page 596: ... a clock with a frequency of 16 8 4 times the bit rate 4 Don t care 14 2 7 Serial Status 1 Register SC1SSR Bit 15 14 13 12 11 10 9 8 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 ER TEND TDFE BRK FER PER RDF DR Initial value 0 1 1 0 0 0 0 0 R W R W R R W R W R R R W R W Note Only 0 can be written to clear the flag The serial status 1 ...

Page 597: ... ER Bit 7 ER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions In a reset or in standby mode When 0 is written to ER after reading ER 1 1 A framing error parity error or overrun error occurred during reception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is...

Page 598: ...ger data number set by bits TTRG1 and TTRG0 in the FIFO control register SCFCR and transmit data can be written to SCFTDR Bit 5 TDFE Description 0 A number of transmit data bytes exceeding the transmit trigger set number have been written to SCFTDR Clearing conditions When transmit data exceeding the transmit trigger set number is written to SCFTDR and 0 is written to TDFE after reading TDFE 1 Whe...

Page 599: ...r is resumed Bit 3 Framing Error FER Indicates a framing error in the data read from the receive FIFO data register SCFRDR Bit 3 FER Description 0 There is no framing error in the receive data read from SCFRDR Initial value Clearing conditions In a reset or in standby mode When there is no framing error in SCFRDR read data 1 There is a framing error in the receive data read from SCFRDR Setting con...

Page 600: ...n SCFRDR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number and 0 is written to RDF after reading RDF 1 When SCFRDR is read by the on chip DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number 1 The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number Setting con...

Page 601: ...er of data bytes Setting condition When SCFRDR contains fewer than the receive trigger set number of receive data bytes and no further data has arrived for at least 16 etu after the stop bit of the last data received 2 Notes 1 All remaining receive data should be read before clearing the DR flag 2 Equivalent to 1 6 frames when using an 8 bit 1 stop bit format etu Elementary time unit sec bit 14 2 ...

Page 602: ...ase clock of 4 times the bit rate 1 SCIF operates on base clock of 8 times the bit rate 1 0 SCIF operates on base clock of 16 times the bit rate Initial value 1 Setting prohibited Bit 3 Multiprocessor bit MPB When reception is performed using a multiprocessor format in asynchronous mode MPB stores the multiprocessor bit in the receive data The MPB flag is read only and cannot be modified Bit 3 MPB...

Page 603: ...tion ER 1 Note When EI 0 only the last data in SCFRDR is treated as data containing an error When EI 1 receive data is sent to SCFRDR even if it contains an error Bit 0 Overrun Error ORER Indicates that an overrun error occurred during reception causing abnormal termination Bit 0 ORER Description 0 Reception in progress or reception has ended normally 1 Initial value Clearing conditions In a reset...

Page 604: ...y the CPU at all times SCBRR is initialized to H FF by a reset by the module standby function and in standby mode The SCBRR setting is found from the following equations Asynchronous mode N 64 22n 1 B 106 1 When operating on a base clock of 16 times the bit rate Pφ N 32 22n 1 B 106 1 When operating on a base clock of 8 times the bit rate Pφ N 16 22n 1 B 106 1 When operating on a base clock of 4 ti...

Page 605: ...N 1 B 64 22n 1 1 100 Pφ 106 When operating on a base clock of 16 times the bit rate Error N 1 B 32 22n 1 1 100 Pφ 106 When operating on a base clock of 8 times the bit rate Error N 1 B 16 22n 1 1 100 Pφ 106 When operating on a base clock of 4 times the bit rate Table 14 3 shows sample SCBRR settings in asynchronous mode and table 14 4 shows sample SCBRR settings in synchronous mode In both tables ...

Page 606: ...16 0 13 2 48 0 15 0 00 0 19 2 34 9600 0 6 6 99 0 6 2 48 0 7 0 00 0 9 2 34 19200 0 2 8 51 0 2 13 78 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 1 4 86 0 1 22 88 0 2 0 00 38400 0 1 18 62 0 1 14 67 0 1 0 00 Pφ φ φ φ MHz 3 6864 4 4 9152 5 Bit Rate Bits s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 ...

Page 607: ... 00 0 23 0 00 0 25 0 16 19200 0 9 2 34 0 9 0 00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 6 5 33 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 0 6 6 99 Pφ φ φ φ MHz 9 8304 10 12 12 288 Bit Rate Bits s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 1...

Page 608: ...64 0 70 3 70 0 03 3 132 0 13 150 2 191 0 00 2 207 0 16 3 97 0 35 300 2 95 0 00 2 103 0 16 2 194 0 16 600 1 191 0 00 1 207 0 16 2 97 0 35 1200 1 95 0 00 1 103 0 16 1 194 0 16 2400 0 191 0 00 0 207 0 16 1 97 0 35 4800 0 95 0 00 0 103 0 16 0 194 0 16 9600 0 47 0 00 0 51 0 16 0 97 0 35 19200 0 23 0 00 0 25 0 16 0 48 0 35 31250 0 14 1 70 0 15 0 00 0 29 0 00 38400 0 11 0 00 0 12 0 16 0 23 1 73 ...

Page 609: ...4 3 249 1 k 1 249 2 124 2 249 3 124 2 5 k 1 99 1 199 2 99 2 199 5 k 0 199 1 99 1 199 2 99 10 k 0 99 0 199 1 99 1 199 25 k 0 39 0 79 0 159 1 79 50 k 0 19 0 39 0 79 0 159 100 k 0 9 0 19 0 39 0 79 250 k 0 3 0 7 0 15 0 31 500 k 0 1 0 3 0 7 0 15 1 M 0 0 0 1 0 3 0 7 2 M 0 0 0 1 0 3 Note As far as possible the setting should be made so that the error is within 1 Legend Blank No setting is available A set...

Page 610: ...it rates when using external clock input Table 14 5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator Asynchronous Mode Settings Pφ φ φ φ MHz Maximum Bit Rate Bits s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 8 250000 0 0 9 8304 307200 0 0 12 375000 0 0 14 7456 460800 0 0 16 500000 0 0 19 66080 614400 0 0 20 6250...

Page 611: ...te Bits s 2 0 5000 31250 2 097152 0 5243 32768 2 4576 0 6144 38400 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 8 2 0000 125000 9 8304 2 4576 153600 12 3 0000 187500 14 7456 3 6864 230400 16 4 0000 250000 30 7 5000 468750 Table 14 7 Maximum Bit Rate with External Clock Input Synchronous Mode Pφ φ φ φ MHz External Input Clock MHz Maximum Bit Rate Bits s 8 1 3333 1333333 3 1...

Page 612: ... the receive data full RDF flag in the serial status 1 register SC1SSR The RDF flag is set when the number of receive data bytes in the receive FIFO data register SCFRDR is equal to or greater than the trigger set number shown in the following table Bit 7 RTRG1 Bit 6 RTRG0 Receive Trigger Number 0 0 1 1 4 1 0 8 1 14 Note Initial value Bits 5 and 4 Transmit FIFO Data Number Trigger TTRG1 TTRG0 Thes...

Page 613: ... Bit 2 TFRST Description 0 Reset operation disabled Initial value 1 Reset operation enabled Note A reset operation is performed in the event of a reset module standby or in standby mode Bit 1 Receive FIFO Data Register Reset RFRST Invalidates the receive data in the receive FIFO data register and resets it to the empty state Bit 1 RFRST Description 0 Reset operation disabled Initial value 1 Reset ...

Page 614: ... 0 0 R W R R R R R R R R Bits 15 to 13 Reserved These bits are always read as 0 The write value should always be 0 Bits 12 to 8 Transmit FIFO Data Count 4 to 0 T4 to T0 These bits show the number of untransmitted data bytes in SCFTDR A value of H 00 indicates that there is no transmit data and a value of H 10 indicates that SCFTDR is full of transmit data The value is cleared to H 00 by transmitti...

Page 615: ...curred When data in the nth stage of the buffer contains an error the nth bit is set to 1 Note that this register is not cleared by setting the RFRST bit to 1 in SCFCR Bits 15 to 0 ED15 to ED0 Description 0 No parity or framing error in data in corresponding stage of register FIFO Initial value 1 Parity or framing error present in data in corresponding stage of register FIFO Note A reset operation...

Page 616: ... to 3 ICK3 to ICK0 of the serial mode register SCSMR Serial Mode Register SCSMR SCIMR Bit 6 ICK3 Bit 5 ICK2 Bit 4 ICK1 Bit 3 ICK0 Bit 2 PSEL Description ICK3 ICK2 ICK1 ICK0 1 Pulse width 3 16 of bit length set in bits ICK3 to ICK0 Don t care Don t care Don t care Don t care 0 Pulse width 3 16 of bit length set in SCBRR Initial value Note A fixed clock pulse signal IRCLK must be generated by multip...

Page 617: ... bits in the serial control register SCSCR as shown in table 14 9 Asynchronous Mode Data length Choice of 7 or 8 bits Choice of parity addition multiprocessor bit addition and addition of 1 or 2 stop bits the combination of these parameters determines the transmit receive format and character length Detection of framing parity and overrun errors receive FIFO data full and receive data ready condit...

Page 618: ...mit Receive Format Selection SCIMR SCSMR Settings SCIF Transmit Receive Format Bit 7 IRMOD Bit 7 C A A A A Bit 6 CHR Bit 2 MP Bit 5 PE Bit 3 STOP Mode Data Length MP Bit Parity Bit Stop Bit Length 0 0 0 0 0 0 Asynchronous 8 bit Absent Absent 1 bit 1 mode data 2 bits 1 0 Present 1 bit 1 2 bits 1 0 0 7 bit Absent 1 bit 1 data 2 bits 1 0 Present 1 bit 1 2 bits 0 1 0 Asynchronous mode multi 8 bit data...

Page 619: ...its indicating the end of communication Serial communication is thus carried out with synchronization established on a character by character basis Inside the SCIF the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also have a 16 stage FIFO buffer structure so that data can be read or written during transmission or reception ...

Page 620: ...t the center of each bit Serial data LSB 7 or 8 bits One unit of transfer data character or frame Parity bit 1 bit or none 1 or 2 bits 1 1 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Idle state mark state Start bit 1 bit MSB Transmit receive data Stop bit s Figure 14 3 Data Format in Asynchronous Communication Example with 8 Bit Data Parity Two Stop Bits LSB First Transfer Transmit Receive Format Table 14 1...

Page 621: ...2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 S 8 bit data STOP 1 S 8 bit data STOP STOP 1 0 S 8 bit data P STOP 1 S 8 bit data P STOP STOP 1 0 0 S 8 bit data STOP 1 S 8 bit data STOP STOP 1 0 S 7 bit data P STOP 1 S 7 bit data P STOP STOP 0 1 0 S 8 bit data MPB STOP 1 S 8 bit data MPB STOP STOP 1 0 S 7 bit data MPB STOP 1 S 7 bit data MPB STOP STOP Note An asterisk in the table means Don t care Legend S Start...

Page 622: ...hen initialize the SCIF as described below When the operating mode communication format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure When the TE bit is cleared to 0 the transmit shift register SCTSR is initialized Note that clearing the TE and RE bits to 0 does not change the contents of the serial status 1 register SC1SSR the transm...

Page 623: ...mmediately after SCSCR settings are made Select input or output for the SCK pin with the PFC 2 Set the transmit receive format in SCSMR When using IrDA mode also set SCIFMR 3 Write a value corresponding to the bit rate into the bit rate register SCBRR Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCSCR to 1 Also set the RIE TIE and MPI...

Page 624: ...reading TDFE 1 The TEND bit is cleared automatically when transmission is started by writing transmit data The number of data bytes that can be written is 16 transmit trigger set number 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE bit to confirm that writing is possible then write data to SCFTDR and then clear the TDFE bit to 0 Checking and clea...

Page 625: ... transmit FIFO data empty interrupt TXI is requested The serial transmit data is sent from the TxD pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first or MSB first order according to the setting of the TLM bit in SC2SSR c Parity bit or multiprocessor bit One parity bit even or odd parity or one multiprocessor bit is output A format ...

Page 626: ...s Mode Example with 8 Bit Data Parity One Stop Bit LSB First Transfer 4 When modem control is enabled transmission can be stopped and restarted in accordance with the CTS input value When CTS is set to 1 if transmission is in progress the line goes to the mark state after transmission of one frame When CTS is set to 0 the next transmit data is output starting from the start bit Figure 14 7 shows a...

Page 627: ... framing error a break can be detected by reading the value of the RxD pin 3 SCIF status check and receive data read Read the serial status 1 register SC1SSR and check that RDF 1 then read receive data from the receive FIFO data register SCFRDR and clear the RDF bit to 0 Transition of the RDF bit from 0 to 1 can also be identified by means of an RXI interrupt 4 Serial reception continuation proced...

Page 628: ...eceive data is not transferred to SCFRDR while the BRK flag is set However note that the H 00 break data in which a framing error occurred is stored as the last data in SCFRDR Error handling Overrun error handling ORER 1 BRK 1 DR 1 FER 1 Framing error handling PER 1 Parity error handling All data read Clear ORER BRK DR and ER flags to 0 End No No No No No No Yes Yes Yes Yes Yes Yes Clear RE bit to...

Page 629: ...c Status check The SCIF checks whether receive data can be transferred from the receive shift register SCRSR to SCFRDR d Break check The SCIF checks that the BRK flag is 0 indicating no break If all the above checks are passed the receive data is stored in SCFRDR If a receive error is detected in the error check the operation is as shown in table 14 11 Note No further receive operations can be per...

Page 630: ...SCRSR to SCFRDR Figure 14 9 shows an example of the operation for reception in asynchronous mode Serial data 1 0 D0 D1 D7 0 1 1 0 D0 D1 D7 0 1 1 1 RDF FER Start bit Parity bit Stop bit Start bit Data Data Parity bit Stop bit Idle state mark state RXI interrupt request One frame Data read and RDF flag cleared to 0 by RXI interrupt handler ERI interrupt request due to framing error Figure 14 9 Examp...

Page 631: ...ansmission cycle which specifies the receiving station and a data transmission cycle The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data wi...

Page 632: ...14 11 Example of Inter Processor Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A Transmit Receive Formats There are four transmit receive formats When the multiprocessor format is specified the parity bit specification is invalid For details see table 14 10 Clock See the section on asynchronous mode Data Transmit Receive Operations SCI Initialization See ...

Page 633: ...FE and TEND flags to 0 after reading 1 from them The number of data bytes that can be written is 16 transmit trigger set number 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE bit to confirm that writing is possible then write data to SCFTDR and then clear the TDFE bit to 0 Checking and clearing of the TDFE bit is automatic when the DMAC is activat...

Page 634: ...s time a transmit FIFO data empty interrupt TXI is requested The serial transmit data is sent from the TxD pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first or MSB first order according to the setting of the TLM bit in SC2SSR c Multiprocessor bit One multiprocessor bit MPBT value is output d Stop bit s One or two 1 bits stop bits ...

Page 635: ... bit Idle state mark state Data written to SCFTDR and TDFE flag cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 14 13 Example of SCIF Transmit Operation Example with 8 Bit Data Multiprocessor Bit One Stop Bit LSB First Transfer Multiprocessor Serial Data Reception Figure 14 14 shows a sample flowchart for multiprocessor serial reception Use the following procedure for ...

Page 636: ...dentify the error After performing the appropriate error handling ensure that ER BRK DR and ORER are all cleared to 0 The setting of the EI bit in SC2SSR determines whether reception is continued or halted when the ORER bit is set to 1 In the case of a framing error a break can be detected by reading the value of the RxD pin 5 SCIF status check and receive data read Read the serial status 1 regist...

Page 637: ... is set However note that the last data in SCFRDR is H 00 and the break data in which a framing error occurred is stored However note that the H 00 break data in which a framing error occurred is stored as the last data in SCFRDR Error handling Clear RE bit to 0 in SCSCR Overrun error handling Read receive data from SCFRDR Framing error handling Clear ORER BRK DR and ER flags to 0 End ORER 1 BRK 1...

Page 638: ... Idle state mark state RXI interrupt request multiprocessor interrupt MPIE 0 SCFRDR data read and RDF flag cleared to 0 by RXI interrupt handler As data is not this station s ID MPIE bit is set to 1 again RXI interrupt request is not generated and SCFRDR retains its state RXI interrupt request multiprocessor interrupt MPIE 0 SCFRDR data read and RDF flag cleared to 0 by RXI interrupt handler As da...

Page 639: ...al communication One unit of transfer data character or frame Serial clock Serial data LSB Bit 0 MSB Don t care Don t care Note High except in continuous transmission reception Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 14 16 Data Format in Synchronous Communication Example of LSB First Transfer In synchronous serial communication data on the communication line is output from one fall of the...

Page 640: ...high In receive only operation however the SCIF receives two characters as one unit and so a 16 pulse serial clock is output To perform single character receive operations an external clock should be selected as the clock source Transmit Receive Operations SCIF Initialization Synchronous Mode Before transmitting and receiving data it is necessary to clear the TE and RE bits to 0 in the serial cont...

Page 641: ...1 in SCSCR and set RIE TIE and MPIE bits Set value in SCBRR 1 bit interval elapsed End 1 Set the clock selection in SCSCR Be sure to clear bits RIE TIE MPIE TE and RE to 0 2 Set the transmit receive format in the serial mode register SCSMR 3 Write a value corresponding to the bit rate into the bit rate register SCBRR Not necessary if an external clock is used 4 Wait at least one bit interval then ...

Page 642: ...All data transmitted Read TEND flag in SC1SSR TEND 1 Clear TE bit to 0 in SCSCR Start of transmission Yes No No No 2 1 3 Yes Yes 1 PFC initialization Set the TxD pin and the SCK pin if necessary with the PFC 2 SCIF status check and transmit data write Read SC1SSR and check that TDFE 1 then write transmit data to the transmit FIFO data register SCFTDR and clear the TDFE flag to 0 3 Serial transmiss...

Page 643: ...ssion the TDFE flag is set If the TIE bit setting in the serial control register SCSCR is 1 at this time a transmit FIFO data empty interrupt TXI is requested When clock output mode has been set the SCIF outputs eight serial clock pulses for one unit of data When use of an external clock has been specified data is output in synchronization with the input clock The serial transmit data is sent from...

Page 644: ...n Example of LSB First Transfer Serial Data Reception Synchronous Mode Figure 14 20 shows a sample flowchart for serial reception Use the following procedure for serial data reception after enabling the SCIF for reception When changing the operating mode from asynchronous to synchronous without resetting SCFRDR and SCFTDR by means of SCIF initialization be sure to check that the ORER PER3 to PER0 ...

Page 645: ...on of the RDF flag from 0 to 1 can also be identified by an RXI interrupt 4 Serial reception continuation procedure To continue serial reception read at least the receive trigger set number of data bytes from SCFRDR and write 0 to the RDF flag after reading 1 from it The number of receive data bytes in SCFRDR can be ascertained by reading the lower 8 bits of the FIFO data count register SCFDR The ...

Page 646: ...checks whether the receive data can be transferred from SCRSR to the receive FIFO data register SCFRDR If this check is passed the receive data is stored in SCFRDR If a receive error is detected in the error check the operation is as shown in table 14 11 Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check Also as the RDF flag...

Page 647: ...t 0 Bit 1 Bit 6 Bit 7 RXI interrupt request ERI interrupt request due to overrun error One frame Figure 14 21 Example of SCIF Receive Operation Example of LSB First Transfer Simultaneous Serial Data Transmission and Reception Synchronous Mode Figure 14 22 shows a sample flowchart for simultaneous serial transmit and receive operations Use the following procedure for simultaneous serial data transm...

Page 648: ...by an RXI interrupt 5 Serial transmission reception continuation procedure To continue serial transmission reception finish reading the RDF flag reading SCFRDR and clearing the RDF flag to 0 before the MSB bit 7 of the current frame is received Also before the MSB bit 7 of the current frame is transmitted read 1 from the TDFE flag to confirm that writing is possible then write data to SCFTDR and c...

Page 649: ...ission and reception The configuration of these buffers is shown in figure 14 23 TxD RxD SCTSR T3 T0 Transmit data writes by CPU or DMAC Receive data reads by CPU or DMAC R3 R0 P P G ED15 ED0 PER3 PER0 SC1SSR FER3 FER0 1st stage 2nd stage 3rd stage Data counter Error counter 16th stage SCFTDR SCFRDR SCFDR SCFER SCRSR P F 16th stage 1st stage 2nd stage 3rd stage Figure 14 23 Transmit Receive FIFO C...

Page 650: ...e FIFO control register SCFCR see section 14 2 10 In Serial Data Receive Operations In reception serial data input from the RxD pin is first captured in the receive shift register SCRSR in the order specified by the RLM bit in the serial status 2 register SC2SSR A parity bit check is carried out and if there is a parity error the P parity error flag for that data is set to 1 A stop bit check is al...

Page 651: ...ified with the EI bit in SC2SSR If the EI bit is set to 1 specifying continuation of the receive operation receive data is still transferred sequentially to the receive FIFO after an error occurs The stage of the 16 stage FIFO buffer in which the data with the error is located can be determined by reading bits ED15 to ED0 in the FIFO error register SCFER When the receive trigger number is set and ...

Page 652: ...de reception is not possible when the TE bit is set to 1 enabling communication in the serial control register SCSCR When performing reception the TE bit in SCSCR must be cleared to 0 Transmission In the case of a serial output signal UART frame from the SCIF the waveform is corrected and the signal is converted to an IR frame serial output signal by the IrDA module as shown in figure 14 24 When t...

Page 653: ... in the IrDA mode register SCIMR The SCIF includes a baud rate generator that generates the transmit frame bit rate and a baud rate generator that generates the IRCLK signal for varying the pulse width When the PSEL bit is cleared to 0 in SCIMR a width of 3 16 the bit rate set in the bit rate register SCBRR is output as the IR frame pulse width As the pulse width is the direct infrared emission ti...

Page 654: ...ulse width IRCLK 921 6 kHz and so the setting for bits ICK3 to ICK0 to give the minimum settable pulse width is given by the following equation N 2 IRCLK 1 Pφ Pφ Operating clock frequency IRCLK 921 6 kHz fixed N Set value of ICK3 to ICK0 0 N 15 For example when Pφ 20 MHz N 10 Table 14 12 shows the settings of bits ICK3 to ICK0 that can be used to obtain the minimum pulse width for various operatin...

Page 655: ...B0292 0200 Table 14 12 Bits ICK3 to ICK0 and Operating Frequencies in IrDA mode When PSEL 1 Operating Frequency Setting of Bits ICK3 to ICK0 in SCSMR Pφ φ φ φ MHz ICK3 ICK2 ICK1 ICK0 2 0 0 0 0 3 1 5 1 0 6 1 8 1 0 0 10 1 12 1 0 14 1 16 1 0 0 0 18 1 20 1 0 21 1 22 1 23 1 0 0 24 1 25 1 26 1 0 27 0 28 1 ...

Page 656: ...atically when all writes to the transmit FIFO data register SCFTDR by the DMAC are completed When the RDF flag is set to 1 in SC1SSR an RXI interrupt is requested An RXI interrupt request can activate the DMAC to perform data transfer The RDF bit is cleared to 0 automatically when all receive FIFO data register SCFRDR reads by the DMAC are completed When the ER flag is set to 1 an ERI interrupt is...

Page 657: ...ried out when SCFTDR contains more than the transmit trigger number of transmit data bytes The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO data count register SCFDR Simultaneous Multiple Receive Errors If a number of receive errors occur at the same time the state of the status flags in SC1SSR and SC2SSR is as shown in table 14 14 If there is an overrun e...

Page 658: ...g is made The initial setting should therefore be as an output port outputting 1 To send a break signal during serial transmission clear DR then set the TxD pin as an output port with the PFC When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state Receive Error Flags and Transmit Operations Synchronous Mode Only Transmission cannot be started whe...

Page 659: ...ynchronous mode can therefore be expressed as shown in equation 1 M 0 5 1 2N D 0 5 N L 0 5 F 1 F 100 1 M Receive margin N Ratio of clock frequency to bit rate N 16 8 or 4 D Clock duty cycle D 0 to 1 0 L Frame length L 9 to 12 F Absolute deviation of clock frequency From equation 1 if F 0 and D 0 5 the receive margin is 46 875 as given by equation 2 When D 0 5 F 0 and N 16 M 0 5 1 2 16 100 46 875 2...

Page 660: ...Pφ cycles after SCFTDR is updated See figure 14 26 When performing SCFRDR reads by the DMAC be sure to set the relevant SCIF receive FIFO data full interrupt RXI as an activation source SCK TDFE TXD D0 D1 D2 D3 D4 D5 D6 t Figure 14 26 Example of Synchronous Transmission by DMAC SCFRDR Reading and the RDF Flag The RDF flag in the serial status 1 register SC1SSR is set when the number of receive dat...

Page 661: ...ontinued despite the fact that the receive FIFO data register SCFRDR contains 16 bytes of data overrun will occur If SCFRDR is read in this state the data that caused the overrun is read in the 17th read The value returned in the 18th and subsequent reads will be undefined Also note that from the first SCFRDR read onward the number of receive data bytes in SCFRDR indicated by the lower 8 bits of t...

Page 662: ...Section 14 Serial Communication Interface with FIFO SCIF Rev 2 00 Mar 09 2006 page 636 of 906 REJ09B0292 0200 ...

Page 663: ...ol register and serial status register receive control data register transmit control data register FIFO control register FIFO data count register With the exception of SIRSR and SITSR these registers are memory mapped and can be accessed by a MOV instruction Choice of 8 or 16 bit data length Data transfer communication by means of polling or interrupts Data transfer can be monitored by polling th...

Page 664: ... register FIFO data count register Bit counter I O control unit Serial I O with FIFO module SIOF Figure 15 1 SIOF Block Diagram Table 15 1 shows the functions of the external pins Table 15 1 Serial I O with FIFO SIOF External Pins Name Pin I O Function Serial receive data input pin SRxD0 Input Serial data input port Serial receive clock input pin SRCK0 Input Serial receive clock port Serial recept...

Page 665: ...FO data count register SIFDR R H 0000 H FFFFFC0A 8 16 32 Note Only 0 should be written to clear flags after reading 1 from the flag 15 2 1 Receive Shift Register SIRSR Bit 15 14 13 3 2 1 0 Initial value R W SIRSR is a 16 bit register used to receive serial data The data is fetched in MSB first from the SRxD pin in synchronization with the fall of the serial receive clock SRCK and is shifted into S...

Page 666: ...is a 16 bit x 16 stage FIFO register that stores primary receive data When primary data is transferred from SIRSR to SIRDR the receive data register full flag RDRF is set in the serial status register SISTR based on the settings of RFWM3 to RFWM0 in SIFCR If the receive interrupt enable flag RIE is set in SICTR a receive data full interrupt RDFI request is sent to the interrupt controller INTC and...

Page 667: ... the transmit control data register SITCDR in this case if the DL bit is cleared to 0 causes the lower 8 bits in SITDR to be output with the LSB as 1 after which the lower 8 bits in SITCDR are output If the DL bit is set to 1 all 16 bits in SITDR are output with the LSB as 1 after which all 16 bits in SITCDR are output When transmit primary data with a value less than or equal to the transmit FIFO...

Page 668: ... T0 in SIFDR is 10000 Data should be written to SITDR in the size specified by the setting of the DL bit in SICTR Always set the TE bit to 1 before writing to this register 15 2 5 Serial Control Register SICTR Bit 15 14 13 12 11 10 9 8 DMACE TCIE RCIE Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W Bit 7 6 5 4 3 2 1 0 TM SE DL TIE RIE TE RE Initial value 0 0 0 0 0 0 0 0 R W R R W R W R W R...

Page 669: ...l value 1 Receive control data register full interrupt enabled Bit 7 Reserved This bit is always read as 0 The write value should always be 0 Bit 6 Transfer Mode Control TM Specifies whether the transmission synchronization signal is to be input from an external source or generated internally by the chip When this flag is cleared the transmission synchronization signal is STS pin input When this f...

Page 670: ...ther should be input to SRS STS between the start and completion of transmission receiving transmit FIFO empty receive FIFO full Bit 4 Transmit Receive Data Length Select DL Specifies the serial I O module s transfer data length The initial value of this bit is 0 indicating an 8 bit data length When an 8 bit data length is specified the lower 8 bits in the receive shift register receive data regis...

Page 671: ...es data reception Bit 0 RE Description 0 Reception disabled Initial value 1 Reception enabled 15 2 6 Serial Status Register SISTR Bit 15 14 9 8 4 3 2 1 0 TCD RCD TERR RERR TDRE RDRF Initial value 0 0 1 0 0 0 0 1 0 R W R R R W R W R R W R W R W R W Note Only 0 should be written to clear the flag SISTR is a 16 bit register that indicates the status of the serial I O module SISTR is initialized to H ...

Page 672: ...D is cleared to 0 in the following cases When 0 is written to RCD after reading RCD 1 When the processor is reset 1 SIRCDR transmit data is valid RCD is set to 1 in the following cases After control data has been received normally and data has been transferred from SIRSR to SIRCDR Bit 7 to 4 Reserved This bit is always read as 0 The write value should always be 0 Bit 3 Transmit Underrun Error TERR...

Page 673: ...ed from SITDR to SITSR and the amount of data inside SITDR is less than or equal to the setting of TFWM3 to TFWM0 in SIFCR Bit 1 TDRE Description 0 Indicates that primary send data exceeding the transmit FIFO watermark setting has been written to SITDR TDRE is cleared to 0 in the following cases When primary send data exceeding the setting of the transmit FIFO watermark bits has been written to SI...

Page 674: ...n SIRDR is greater than or equal to the receive FIFO watermark setting RDRF is set to 1 in the following cases When the received primary data stored in SIRDR is greater than or equal to the receive FIFO watermark setting 15 2 7 Receive Control Data Register SIRCDR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R SIRCDR is a...

Page 675: ...STS goes high and primary data bit 0 is transmitted as 1 When STS next goes high the control data stored in SITCDR is transferred to SITSR If the TCD bit is 0 at this point and TCD bit is set to 1 After this the control data previously transferred from SITCDR to SITSR is transmitted If the TRMD bit is cleared to 0 no control data is transmitted even if data is written to SITCDR If the TCD bit in S...

Page 676: ...tely precedes control data Note If the TRMD bit is set to 1 in SICTR the TM bit STS pin input should be cleared to 0 the SE bit interval mode set to 1 and the LM bit transmit receive MSB format cleared to 0 The sync signal output from the connected codec should be input to pins STS and SRS The serial clock output from the connected codec should be input to pins STCK and SRCK Bit 10 LSB MSB First S...

Page 677: ... value 1 Reset enabled Note Reset status persists while this bit is set to 1 Clear this bit to 0 to cancel reset status Bit 7 to 4 Receive FIFO Watermark RFWM3 to RFWM0 These bits are used to make threshold settings which are used to set the RDRF bit in SISTR When the amount of primary receive data in SIRDR is equal to or greater than the watermark setting as shown in the table below the RDRF bit ...

Page 678: ...d settings which are used to set the TDRE bit in SISTR When the amount of primary send data in SITDR is less than or equal to the watermark setting as shown in the table below the TDRE bit is set to 1 Bit 3 TFWM3 Bit 2 TFWM2 Bit 1 TFWM1 Bit 0 TFWM0 Watermark setting 0 0 0 0 0 Initial value 1 1 1 0 2 1 3 1 0 0 4 1 5 1 0 6 1 7 1 0 0 0 8 1 9 1 0 10 1 11 1 0 0 12 1 13 1 0 14 1 15 ...

Page 679: ...ways read as 0 Bit 12 to 8 Receive Data Register Data Count Bits 4 to 0 R4 to R0 These bits indicate the amount of primary receive data stored in SIRDR When the value of bits R4 to R0 is H 00 there is no primary receive data stored in SIRDR and when the value is H 10 SIRDR is full In addition to the initialized status mentioned above bits R4 to R0 can be cleared to H 00 by reading all the primary ...

Page 680: ...0 in SICTR with MSB first LM cleared to 0 in SIFCR Note DL 0 8 bit data transfer SE 1 Synchronous transfer in start signal mode LM 0 MSB first TRMD 0 LSB of transmitted primary data is value in SITDR B 7 A 7 A 7 0 A 7 0 A 7 6 A 7 1 Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received A 7 A 6 A 5 A 0 B 7 B 6 Invalid SRXD SRS SRCK SIRSR SIR...

Page 681: ...SRXD SRS SRCK SIRSR SIRDR RDRF Note DL 0 8 bit data transfer SE 0 Asynchronous transfer no start signal mode LM 0 MSB first TRMD 0 LSB of transmitted primary data is value in SITDR Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received Synchronous internal clock Figure 15 3 Reception Continuous Transfer Mode MSB First ...

Page 682: ...ted primary data is value in SITDR Set to 1 when an amount of data equal to or greater than the setting of bits RFWM3 to RFWM0 in SIFCR is received Synchronous internal clock Undefined Figure 15 4 Reception Interval Transfer Mode LSB First SRXD SRS SRCK SIRSR SIRDR RDRF A 0 A 1 A 2 A 7 B 0 B 1 B 2 B 3 B 0 A 0 A 0 7 A 7 0 B 0 1 B 0 2 A 0 1 A 0 6 Note DL 0 8 bit data transfer SE 0 Asynchronous trans...

Page 683: ...M is set to 1 in SICTR and with MSB first STXD STS STCK SITSR SITDR TDRE C 7 0 C 6 0 C 5 0 C 0 C 7 0 D 7 0 D 7 0 E 7 0 Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR C 7 C 6 C 5 C 0 D 7 D 6 D 7 0 D 6 0 Note TM 0 STS is input DL 0 8 bit data transfer SE 1 Synchronous transfer in start signal mode LM 0 MSB first TRMD 0 LSB of transmitte...

Page 684: ...0 in SIFCR has been written to SITDR Synchronous internal clock Undefined Figure 15 7 Transmission Continuous Transfer Mode TM 0 Mode MSB First STXD STS STCK SITSR SITDR C 7 0 C 6 0 C 5 0 C 7 0 D 7 0 D 7 0 E 7 0 C 1 0 C 0 D 7 0 C 7 C 6 C 5 C 0 D 7 C 1 D 6 D 5 D 6 0 D 5 0 SITDR TDRE Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR Note T...

Page 685: ...MD 0 LSB of transmitted primary data is value in SITDR Cleared to 0 when an amount of data exceeding the setting of bits TFWM3 to TFWM0 in SIFCR has been written to SITDR Synchronous internal clock Undefined Figure 15 9 Transmission Continuous Transfer Mode TM 1 Mode MSB First Figure 15 10 shows interval transfer mode when TM is cleared to 0 in SICTR and with LSB first Figure 15 11 shows continuou...

Page 686: ...CR has been written to SITDR Synchronous internal clock Undefined Figure 15 10 Transmission Interval Transfer Mode TM 0 Mode LSB First STXD STS STCK SITSR SITDR TDRE C 0 7 C 1 7 C 2 7 C 7 0 D 7 0 D 7 0 E 7 0 C 7 D 0 7 D 1 7 C 0 C 1 C 2 D 0 D 1 C 7 D 2 D 3 D 2 7 D 3 7 Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR Note TM 0 STS is inpu...

Page 687: ...s internal clock Undefined Figure 15 12 Transmission Interval Transfer Mode TM 1 Mode LSB First STXD STS STCK SITSR SITDR TDRE C 0 7 C 1 7 C 2 7 C 7 0 D 7 0 D 7 0 E 7 0 C 7 D 0 7 D 1 7 C 0 C 1 C 2 D 0 D 1 C 7 D 2 D 3 D 2 7 D 3 7 Set to 1 when the amount of data in SITDR is less than or equal to the setting of bits TFWM3 to TFWM0 in SIFCR Note TM 1 STS is output DL 0 8 bit data transfer SE 0 Asynch...

Page 688: ... D 7 0 D 6 0 D 0 D 7 0 E 7 0 E 7 0 F 7 0 F 7 0 F 7 0 D 7 D 6 D 0 E 7 E 6 E 0 Z 7 Z 6 Z 0 STXD STS STCK SITSR SITDR TDRE SITCDR Undefined E 6 0 Z 7 0 Z 7 0 Z 7 0 Z 7 0 Z 6 0 Z 7 0 E 0 F 7 0 Z 0 Note TM 0 STS is input DL 0 8 bit data transfer SE 1 Synchronous transfer in start signal mode LM 0 MSB first TRMD 1 LSB of transmitted primary data is 0 Set to 1 when the amount of data in SITDR is less tha...

Page 689: ...This will cause interrupts triggered by the RDRF bit to be sent to the DMAC and interrupts triggered by the RCD bit to be sent to the INTC The data in SIRDR is read and if the amount of primary data is less than the setting of bits RFWM3 to RFWM0 in SIFCR RDRF is automatically cleared to 0 Interrupts triggered by the RCD bit cannot be processed by the DMAC An TDEI0 interrupt request is generated w...

Page 690: ...ble TDEI0 Transmit data register empty TDRE Transmit Control Data Register Empty TCD Possible Low Note The interrupt sources that can activate the DMAC are receive data full RDRF and transmit data empty TDRE It is not possible for receive control data full RCD or transmit control data empty TCD to activate the DMAC The DMAC should be used to process RDRF and TDRE interrupts when using SIRCDR and S...

Page 691: ...terval transfer mode and continuous transfer mode Memory mapped receive register transmit register control register and status register With the exception of SIRSR and SITSR these registers are memory mapped and can be accessed by a MOV instruction Choice of 8 or 16 bit data length Data transfer communication by means of polling or interrupts Data transfer can be monitored by polling the receive d...

Page 692: ...SICTR STCK SRCK SRxD SIRDR Receive data register SIRSR Receive shift register SISTR Serial status register SICTR Serial control register SITDR Transmit data register SITSR Transmit shift register Bit counter I O control unit SIRSR SITSR STxD SRS STS MSB LSB MSB LSB Serial I O module SIO Figure 16 1 SIO Block Diagram ...

Page 693: ...utput Serial data output port 1 Serial transmit clock input pin STCK1 Input Serial transmit clock port 1 Serial transmission synchro nization input output pin STS1 I O Serial transmission synchro nization input output port 1 2 Serial receive data input pin SRxD2 Input Serial data input port 2 Serial receive clock input pin SRCK2 Input Serial receive clock port 2 Serial reception synchronization in...

Page 694: ... H 0000 H FFFFFC10 8 16 32 Transmit shift register 1 SITSR1 Transmit data register 1 SITDR1 R W H 0000 H FFFFFC12 8 16 32 Serial control register 1 SICTR1 R W H 0000 H FFFFFC14 8 16 32 Serial status register 1 SISTR1 R W H 0002 H FFFFFC16 8 16 32 2 Receive shift register 2 SIRSR2 Receive data register 2 SIRDR2 R H 0000 H FFFFFC20 8 16 32 Transmit shift register 2 SITSR2 Transmit data register 2 SI...

Page 695: ...t data word input operation ends before the RDRF flag is cleared an overrun error occurs the receive overrun error flag RERR is set in SISTR and an overrun error signal is sent to the interrupt controller INTC The data in SIRSR overwrites the data in SIRDR 16 2 2 Receive Data Register SIRDR Bit 15 14 13 3 2 1 0 Initial value 0 0 0 0 0 0 0 R W R R R R R R R SIRDR is a 16 bit register that stores se...

Page 696: ...t data begins before TDRE is cleared an overrun error occurs the transmit overrun error flag TERR is set in SISTR and a transmit overrun error interrupt request is sent to the INTC 16 2 4 Transmit Data Register SITDR Bit 15 14 13 3 2 1 0 Initial value 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W SITDR is a 16 bit register that stores serial transmit data Data should be written to SITDR when the t...

Page 697: ...ion synchronization signal is STS pin input When this flag is set the transmission synchronization signal is generated by the chip and is output to an external device from the STS pin This bit does not affect reception Bit 6 TM Description 0 External signal input from STS pin is used as transmission start indication Initial value 1 Internal signal output from STS pin is used as transmission start ...

Page 698: ...pt disabled Initial value 1 Transmit interrupt enabled Bit 2 Receive Interrupt Enable RIE Enables the receive data full interrupt The initial value of this bit is 0 Bit 2 RIE Description 0 Receive interrupt disabled Initial value 1 Receive interrupt enabled Bit 1 Transmit Enable TE Enables data transmission When this flag is cleared the STxD STCK and STS pins go to the high impedance state Bit 1 T...

Page 699: ...occurrence of a transmit underrun Bit 3 TERR Description 0 Transmission is in progress or has ended normally Initial value Clearing conditions When 0 is written to the TERR bit after reading TERR 1 When the processor enters the reset state 1 A transmit underrun error has occurred TERR is set to 1 if data transmission is started while TDRE 1 Bit 2 Receive Overrun Error RERR Flag that indicates the ...

Page 700: ...en data is transferred from SITDR to SITSR When the TE bit is cleared to 0 in the serial control register SICTR When the processor enters the reset state Bit 0 Receive Data Register Full RDRF Flag that indicates that SIRDR receive data is waiting Bit 0 RDRF Description 0 SIRDR receive data is invalid Initial value Clearing conditions When the DMAC reads data from SIRDR When 1 is read from RDRF and...

Page 701: ...E 1 Synchronous transfer in start signal mode SRS SRCK A 7 SIRSR A 7 0 A 7 6 A 7 1 A 7 0 SIRDR RDRF A 7 A 6 A 5 A 0 A 1 B 7 synchronous internal clock Undefined Invalid Figure 16 2 Reception Interval Transfer Mode SRxD Notes DL 0 8 bit data transfer SE 0 Asynchronous transfer no start signal mode SRCK SRS A 7 A 6 A 5 A 0 B 7 B 6 B 5 A 1 SIRSR B 7 A 7 A 7 0 B 7 6 B 7 5 A 7 6 A 7 1 A 7 0 SIRDR RDRF ...

Page 702: ...CTR Figure 16 6 shows interval transfer mode SE set to 1 in SICTR when TM is set to 1 in SICTR Figure 16 7 shows continuous transfer mode SE cleared to 0 in SICTR when TM is set to 1 in SICTR STxD Notes TM 0 STS is input DL 0 8 bit data transfer SE 1 Synchronous transfer in start signal mode STCK STS C 7 C 6 C 5 C 0 D 7 C 1 SITSR C 6 0 C 7 0 D 7 0 D 6 0 C 5 0 C 0 Data C SITDR TDRE synchronous inte...

Page 703: ... D 6 0 D 5 0 D 4 0 C 5 0 C 0 SITDR TDRE synchronous internal clock Undefined Data C Figure 16 5 Transmission Continuous Transfer Mode TM 0 Mode C 6 0 STxD Notes TM 1 STS is output DL 0 8 bit data transfer SE 1 Synchronous transfer in start signal mode STCK STS C 7 C 6 C 5 C 0 D 7 C 1 C 7 0 SITSR D 7 0 D 6 0 C 5 0 Data C SITDR TDRE synchronous internal clock Undefined C 0 Invalid Data D Figure 16 6...

Page 704: ...s TM 1 STS is output DL 0 8 bit data transfer SE 0 Asynchronous transfer no start signal mode STCK STS C 7 C 6 C 5 C 0 D 7 D 6 D 5 C 1 C 7 0 SITSR D 7 0 D 6 0 D 5 0 D 4 0 C 5 0 C 0 Data C SITDR TDRE synchronous internal clock Undefined Figure 16 7 Transmission Continuous Transfer Mode TM 1 Mode ...

Page 705: ...interrupt request is generated when the TDRE bit is set to 1 in SISTR TDEI can activate the DMAC to write the next data to SITDR TDRE is cleared to 0 automatically when the DMAC writes data to SITDR When TDEI and RDFI interrupt requests are handled by the DMAC and not by the interrupt controller a low priority level should be given to interrupts from the SIO to prevent the interrupt controller fro...

Page 706: ...Section 16 Serial I O SIO Rev 2 00 Mar 09 2006 page 680 of 906 REJ09B0292 0200 ...

Page 707: ...e of rising edge falling edge or both edge detection Counter clear operation Counter clearing possible by compare match or input capture Synchronous operation Multiple timer counters TCNT can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input output possible by counter synchronous operation PWM mode Any PWM output duty can be ...

Page 708: ...annel 0 Channel 1 Channel 2 Count clock Pφ 1 Pφ 4 Pφ 16 Pφ 64 TCLKA TCLKB TCLKC TCLKD Pφ 1 Pφ 4 Pφ 16 Pφ 64 Pφ 256 TCLKA TCLKB Pφ 1 Pφ 4 Pφ 16 Pφ 64 Pφ 1024 TCLKA TCLKB TCLKC General registers TGR0A TGR0B TGR1A TGR1B TGR2A TGR2B General registers buffer registers TGR0C TGR0D I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Counter clear function TGR compare match or input capture T...

Page 709: ...terrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 sources Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow Note Not possible ...

Page 710: ...KB TCLKC TCLKD I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 0 Channel 1 Channel 2 Internal data bus TIORL Module data bus TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Internal clock External clock Channel 0 Channel 1 Channel 2 TCR Timer Control Register TMDR Timer Mode Register TIOR Timer I O Control Register TI...

Page 711: ... A0 TIOCA0 I O TGR0A input capture input output compare output PWM output pin Input capture output compare match B0 TIOCB0 I O TGR0B input capture input output compare output PWM output pin Input capture output compare match C0 TIOCC0 I O TGR0C input capture input output compare output PWM output pin Input capture output compare match D0 TIOCD0 I O TGR0D input capture input output compare output P...

Page 712: ... Timer status register 0 TSR0 R W H C0 H FFFFFC55 8 16 Timer counter 0 TCNT0 R W H 0000 H FFFFFC56 16 Timer general register 0A TGR0A R W H FFFF H FFFFFC58 16 Timer general register 0B TGR0B R W H FFFF H FFFFFC5A 16 Timer general register 0C TGR0C R W H FFFF H FFFFFC5C 16 Timer general register 0D TGR0D R W H FFFF H FFFFFC5E 16 1 Timer control register 1 TCR1 R W H 00 H FFFFFC60 8 16 Timer mode re...

Page 713: ...2 TCNT2 R W H 0000 H FFFFFC76 16 Timer general register 2A TGR2A R W H FFFF H FFFFFC78 16 Timer general register 2B TGR2B R W H FFFF H FFFFFC7A 16 All Timer start register TSTR R W H 00 H FFFFFC40 8 16 Timer synchro register TSYR R W H 00 H FFFFFC41 8 16 Note Only 0 can be written to clear the flags 17 2 Register Descriptions 17 2 1 Timer Control Register TCR Channel 0 TCR0 Bit 7 6 5 4 3 2 1 0 CCL...

Page 714: ...ous operation 1 1 0 0 TCNT clearing disabled 1 TCNT cleared by TGRC compare match input capture 2 1 0 TCNT cleared by TGRD compare match input capture 2 1 TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 1 Channel Bit 7 Reserved 3 Bit 6 CCLR1 Bit 5 CCLR0 Description 1 2 0 0 0 TCNT clearing disabled Initial value 1 TCNT cleared by TGRA compa...

Page 715: ...ored and a rising edge count is selected Bits 2 to 0 Time Prescaler 2 to 0 TPSC2 to TPSC0 These bits select the TCNT counter clock The clock source can be selected independently for each channel Table 17 4 shows the clock sources that can be set for each channel Table 17 4 TPU Clock Sources Internal Clock External Clock Channel Pφ φ φ φ 1 Pφ φ φ φ 4 Pφ φ φ φ 16 Pφ φ φ φ 64 Pφ φ φ φ 256 Pφ φ φ φ 10...

Page 716: ...nel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock counts on Pφ 1 Initial value 1 Internal clock counts on Pφ 4 1 0 Internal clock counts on Pφ 16 1 Internal clock counts on Pφ 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKB pin input 1 0 External clock counts on TCLKC pin input 1 Internal clock counts on Pφ 1024 Note This setting is ignor...

Page 717: ...ether for buffer operation When TGRD is used as a buffer register TGRD input capture output compare is not generated In channels 1 and 2 which have no TGRD bit 5 is reserved It is always read as 0 and cannot be modified Bit 5 BFB Description 0 TGRB operates normally Initial value 1 TGRB and TGRD used together for buffer operation Bit 4 Buffer Operation A BFA Specifies whether TGRA is to operate in...

Page 718: ... a reserved bit In a write it should always be written with 0 2 Phase counting mode cannot be set for channel 0 In this case 0 should always be written to MD2 17 2 3 Timer I O Control Register TIOR Channel 0 TIOR0H Channel 1 TIOR1 Channel 2 TIOR2 Bit 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Channel 0 TIOR0L Bit 7 6 5 ...

Page 719: ...to 4 I O Control B3 to B0 IOB3 to IOB0 I O Control D3 to D0 IOD3 to IOD0 Bits IOB3 to IOB0 specify the function of TGRB Bits IOD3 to IOD0 specify the function of TGRD TIOR0H Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 0 0 0 0 0 TGR0B is Output disabled Initial value 1 output Initial output is 0 0 output at compare match 1 0 compare output 1 output at compare match 1 register To...

Page 720: ...oggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 Capture input Input capture at rising edge 1 source is Input capture at falling edge 1 TIOCD0 pin Input capture at both edges 1 TGR0D is input capture register 1 Setting prohibited Don t care Note 1 When the BFB bit in TMD...

Page 721: ...pture at rising edge 1 input source is Input capture at falling edge 1 capture TIOCB1 pin Input capture at both edges 1 register Setting prohibited Don t care TIOR2 Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 2 0 0 0 0 TGR2B is Output disabled Initial value 1 output Initial output is 0 0 output at compare match 1 0 compare output 1 output at compare match 1 register Toggle outp...

Page 722: ...0 0 0 0 0 TGR0A is Output disabled Initial value 1 output Initial output is 0 0 output at compare match 1 0 compare output 1 output at compare match 1 register Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 TGR0A is Capture input Input capture at rising edge 1 input s...

Page 723: ...oggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 0 Capture input Input capture at rising edge 1 source is Input capture at falling edge 1 TIOCC0 pin Input capture at both edges 1 TGR0C is input capture register 1 Setting prohibited Don t care Note 1 When the BFA bit in TMD...

Page 724: ...pture at rising edge 1 input source is Input capture at falling edge 1 capture TIOCA1 pin Input capture at both edges 1 register Setting prohibited Don t care TIOR2 Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 2 0 0 0 0 TGR2A is Output disabled Initial value 1 output Initial output is 0 0 output at compare match 1 0 compare output 1 output at compare match 1 register Toggle outp...

Page 725: ...ed to H 40 by a reset Bit 7 Reserved This bit is always read as 0 The write value should always be 0 Bit 6 Reserved This bit is always read as 1 The write value should always be 1 Bit 5 Underflow Interrupt Enable TCIEU Enables or disables interrupt requests TCIU by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2 In channel 0 bit 5 is reserved It is always read as 0 and cann...

Page 726: ...TSR is set to 1 in channel 0 In channels 1 and 2 bit 2 is reserved It is always read as 0 and cannot be modified Bit 2 TGIEC Description 0 Interrupt requests TGIC by TGFC bit disabled Initial value 1 Interrupt requests TGIC by TGFC bit enabled Bit 1 TGR Interrupt Enable B TGIEB Enables or disables interrupt requests TGIB by the TGFB bit when the TGFB bit in TSR is set to 1 Bit 1 TGIEB Description ...

Page 727: ...R W R R R W R W R R R W R W Note Only 0 can be written to clear the flags The TSR registers are 8 bit registers that indicate the status of each channel The TPU has three TSR registers one for each channel The TSR registers are initialized to H C0 by a reset Bit 7 Count Direction Flag TCFD Status flag that shows the direction in which TCNT counts in channels 1 and 2 In channel 0 bit 7 is reserved ...

Page 728: ...FV Description 0 Clearing condition Initial value When 0 is written to TCFV after reading TCFV 1 1 Setting condition When the TCNT value overflows changes from H FFFF to H 0000 Bit 3 Input Capture Output Compare Flag D TGFD Status flag that indicates the occurrence of TGRD input capture or compare match in channel 0 In channels 1 and 2 bit 3 is reserved It is always read as 0 and cannot be modifie...

Page 729: ...g conditions When TCNT TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register Bit 1 Input Capture Output Compare Flag B TGFB Status flag that indicates the occurrence of TGRB input capture or compare match Bit 1 TGFB Description 0 Clearing conditions Initial value When DMAC is acti...

Page 730: ...input capture signal while TGRA is functioning as input capture register 17 2 6 Timer Counter TCNT Channel 0 TCNT0 up counter Channel 1 TCNT1 up down counter Channel 2 TCNT2 up down counter Bit 15 14 13 12 11 10 9 8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note These counters can be used ...

Page 731: ...o be designated for operation as buffer registers The TGR registers are initialized to H FFFF by a reset The TGR registers cannot be accessed in 8 bit units they must always be accessed as a 16 bit unit Note TGR buffer register combinations are TGRA TGRC and TGRB TGRD 17 2 8 Timer Start Register TSTR Bit 7 6 5 4 3 2 1 0 CST2 CST1 CST0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R W R W R W TSTR is...

Page 732: ...on for the channel 0 to 2 TCNT counters A channel performs synchronous operation when the corresponding bit in TSYR is set to 1 TSYR is initialized to H 00 by a reset Bits 7 to 3 Reserved These bits are always read as 0 The write value should always be 0 Bits 2 to 0 Timer Synchro 2 to 0 SYNC2 to SYNC0 These bits select whether operation is independent of or synchronized with other channels When sy...

Page 733: ...ot be read or written to in 8 bit units 16 bit access must always be used An example of 16 bit register access operation is shown in figure 17 2 Bus interface H Internal data bus L Bus master Module data bus TCNTH TCNTL Figure 17 2 16 Bit Register Access Operation Bus Master TCNT 16 Bits 17 3 2 8 Bit Registers Registers other than TCNT and TGR are 8 bit As the data bus to the CPU is 16 bits wide t...

Page 734: ...data bus L Module data bus TCR Bus master Figure 17 3 8 Bit Register Access Operation Bus Master TCR Upper 8 Bits Bus interface H Internal data bus L Module data bus TMDR Bus master Figure 17 4 8 Bit Register Access Operation Bus Master TMDR Lower 8 Bits Bus interface H Internal data bus L Module data bus TCR TMDR Bus master Figure 17 5 8 Bit Register Access Operation Bus Master TCR and TMDR 16 Bi...

Page 735: ...e by setting the counter clear bits in TCR for channels designated for synchronous operation Buffer Operation When TGR is an output compare register When a compare match occurs the value in the buffer register for the relevant channel is transferred to TGR When TGR is an input capture register When input capture occurs the value in TCNT is transfer to TGR and the value previously held in TGR is tr...

Page 736: ...g source Periodic counter Set period Start count operation Periodic counter 1 2 4 3 5 Free running counter Start count operation Free running counter 5 1 2 3 4 5 Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodic counter operation select the TGR to be used as the TCNT clearing source with bits CCLR2 to...

Page 737: ...free running counter operation TCNT value H FFFF H 0000 CST bit TCFV Time Figure 17 7 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bi...

Page 738: ...g procedure for waveform output by compare match Figure 17 9 shows an example of the setting procedure for waveform output by compare match Select waveform output mode Output selection Set output timing Start count operation Waveform output 1 1 2 3 2 3 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value ...

Page 739: ...evel does not change TCNT value H FFFF H 0000 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 17 10 Example of 0 Output 1 Output Operation Figure 17 11 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing performed by compare match B and settings have been made so that output is toggled by...

Page 740: ...ut capture operation setting procedure Figure 17 12 shows an example of the input capture operation setting procedure Select input capture input Input selection Start count Input capture operation 1 1 2 2 Designate TGR as an input capture register by means of TIOR and select rising edge falling edge or both edges as the input capture source and input signal edge Set the CST bit in TSTR to 1 to sta...

Page 741: ...nd falling edges have been selected as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT value H 0180 H 0000 TIOCA TGRA Time H 0010 H 0005 Counter cleared by TIOCB input falling edge H 0160 H 0005 H 0160 H 0010 TGRB H 0180 TIOCB Figure 17 13 Example of Input Ca...

Page 742: ...ation selection Set TCNT Synchronous presetting Synchronous presetting 1 2 Synchronous clearing Select counter clearing source Counter clearing 3 Start count 5 Set synchronous counter clearing Synchronous clearing 4 Start count 5 Clearing source generation channel No Yes 1 2 3 4 5 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation When the TCNT ...

Page 743: ...ous clearing has been set for the channel 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearing by TGR0B compare match is performed for channel 0 to 2 TCNT counters and the data set in TGR0B is used as the PWM cycle For details of PWM modes see section 17 4 5 PWM Modes TCNT0 to TCNT2 valu...

Page 744: ...er Table 17 5 shows the register combinations used in buffer operation Table 17 5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D When TGR is an output compare register When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register This operation is illustrate...

Page 745: ...ral register TCNT Input capture signal Figure 17 17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 17 18 shows an example of the buffer operation setting procedure Select TGR function Buffer operation Set buffer operation Start count Buffer operation 1 1 2 2 3 3 Designate TGR as an input capture register or output compare register by means of TIOR Designate TGR...

Page 746: ...re TCNT clearing by compare match B 1 output at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA This operation is repeated each time compare match A occurs For details of PWM modes see section 17 4 5 PWM Modes TCNT value ...

Page 747: ...NT value is stored in TGRA upon occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC TCNT value H 09FB H 0000 TGRC Time H 0532 TIOCA TGRA H 0F07 H 0532 H 0F07 H 0532 H 0F07 H 09FB Figure 17 20 Example of Buffer Operation 2 17 4 5 PWM Modes In PWM mode PWM waveforms are output from the output pins 0 1 or toggle output can be selected as the output ...

Page 748: ...e cycle register and the others as duty registers The output specified by TIOR is performed in response to a compare match Also when the counter is cleared by a synchronization register compare match pin output values are the initial values set in TIOR If the set values of the period and duty registers are identical the output value does not change when a compare match occurs In PWM mode 2 a maxim...

Page 749: ... used as the TCNT clearing source Use TIOR to designate the TGR as an output compare register and select the initial value and output value Set the cycle in the TGR selected in 2 and set the duty in the other the TGR Select the PWM mode with bits MD3 to MD0 in TMDR Set the CST bit in TSTR to 1 to start the count operation Figure 17 21 Example of PWM Mode Setting Procedure Examples of PWM Mode Oper...

Page 750: ...tion is designated for channels 0 and 1 TGR1B compare match is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers to output a 5 phase PWM waveform In this case the value set in TGR1B is used as the cycle and the values set in the other TGRs as the duty TCNT value TGR1B H 0000 TIOCA0 Counter cleared by TGR1B compare match ...

Page 751: ...tten TGRB rewritten TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneousl...

Page 752: ...ng up the TCFV flag in TSR is set when underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or down Table 17 7 shows the correspondence between external clock pins and channels Table 17 7 Phase Counting Mode Clock Input Pins External Clock Pins Channels A Phase B...

Page 753: ...ows an example of phase counting mode 1 operation and table 17 8 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 17 26 Example of Phase Counting Mode 1 Operation Table 17 8 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channel 1 TCLKC Channel 2 High level Low level High level Low level...

Page 754: ...t Up count TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Figure 17 27 Example of Phase Counting Mode 2 Operation Table 17 9 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channel 1 TCLKC Channel 2 High level Low level High level Low level Notes Rising edge Falling edge TCLKB Channel 1 TCLKD Channel 2 Low level High level High level Low level Operation Don t care Don t ca...

Page 755: ...TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Down count Figure 17 28 Example of Phase Counting Mode 3 Operation Table 17 10 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channel 1 TCLKC Channel 2 High level Low level High level Low level Notes Rising edge Falling edge TCLKB Channel 1 TCLKD Channel 2 Low level High level High level Low level Operation Don t care Don t c...

Page 756: ...e TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Up count Down count TCNT value Figure 17 29 Example of Phase Counting Mode 4 Operation Table 17 11 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channel 1 TCLKC Channel 2 High level Low level High level Low level Notes Rising edge Falling edge TCLKB Channel 1 TCLKD Channel 2 Low level High level High level Low level Operat...

Page 757: ...ity order within a channel is fixed For details see section 5 Interrupt Controller INTC Table 17 12 lists the TPU interrupt sources Table 17 12 TPU Interrupts Channel Interrupt Source Description DMAC Activation Priority 0 TGI0A TGR0A input capture compare match Possible High TGI0B TGR0B input capture compare match Possible TGI0C TGR0C input capture compare match Possible TGI0D TGR0D input capture...

Page 758: ...SR is set to 1 by the occurrence of TCNT overflow on a particular channel The interrupt request is cleared by clearing the TCFV flag to 0 The TPU has three overflow interrupts one for each channel Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on channel The interrupt request is cleared by...

Page 759: ...unt timing in internal clock operation and figure 17 31 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock Pφ N 1 N N 1 N 2 Falling edge Rising edge Figure 17 30 Count Timing in Internal Clock Operation TCNT TCNT input clock External clock Pφ N 1 N N 1 N 2 Rising edge Falling edge Falling edge Figure 17 31 Count Timing in External Clock Operation ...

Page 760: ...et in TIOR is output at the output compare output pin TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 17 32 shows output compare output timing TGR TCNT TCNT input clock Pφ N N N 1 Compare match signal TIOC pin Figure 17 32 Output Compare Output Timing Input Capture Signal Timing Figure 17 33 shows input capture si...

Page 761: ...hen counter clearing by compare match occurrence is specified and figure 17 35 shows the timing when counter clearing by input capture occurrence is specified TCNT Counter clear signal Compare match signal Pφ TGR N N H 0000 Figure 17 34 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal Pφ TGR N H 0000 N Figure 17 35 Counter Clear Timing Input Capture ...

Page 762: ...ration Timing Figures 17 36 and 17 37 show the timing in buffer operation TGRA TGRB Compare match signal TCNT Pφ TGRC TGRD n N N n n 1 Figure 17 36 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal Pφ TGRC TGRD N n n N 1 N N N 1 Figure 17 37 Buffer Operation Timing Input Capture ...

Page 763: ...Timing TGF Flag Setting Timing in Case of Compare Match Figure 17 38 shows the timing for setting of the TGF flag in TSR by compare match occurrence and TGI interrupt request signal timing TGR TCNT TCNT input clock Pφ N N N 1 Compare match signal TGF flag TGI interrupt Figure 17 38 TGI Interrupt Timing Compare Match ...

Page 764: ...Pφ N N TGF flag TGI interrupt Figure 17 39 TGI Interrupt Timing Input Capture TCFV Flag TCFU Flag Setting Timing Figure 17 40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence and TCIV interrupt request signal timing Figure 17 41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overf...

Page 765: ... Clearing Timing After a status flag is read as 1 by the CPU it is cleared by writing 0 to it When the DMAC is activated the flag is cleared automatically Figure 17 42 shows the timing for status flag clearing by the CPU and figure 17 43 shows the timing for status flag clearing by the DMAC Status flag Write signal Address Pφ TSR address Interrupt request signal TSR write cycle T1 T2 Figure 17 42 ...

Page 766: ... in the case of single edge detection and at least 2 5 states in the case of both edge detection The TPU will not operate properly with a narrower pulse width In phase counting mode the phase difference and overlap between the two input clocks must be at least 1 5 states and the pulse width must be at least 2 5 states Figure 17 44 shows the input clock conditions in phase counting mode Overlap Pha...

Page 767: ...ter frequency is given by the following formula f Pφ N 1 Where f Counter frequency Pφ Peripheral module clock N TGR set value Contention between TCNT Write and Clear Operations If the counter clear signal is generated in the T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 17 45 shows the timing in this case Counter clear signal Write signal ...

Page 768: ...rations If incrementing occurs in the T2 state of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 17 46 shows the timing in this case TCNT input clock Write signal Address Pφ TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 17 46 Contention between TCNT Write and Increment Operations ...

Page 769: ...GR write cycle the TGR write takes precedence and the compare match signal is inhibited A compare match does not occur even if the same value as before is written Figure 17 47 shows the timing in this case Compare match signal Write signal Address Pφ TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Inhibited Figure 17 47 Contention between TGR Write and Compare Match ...

Page 770: ...urs in the T2 state of a TGR write cycle the data transferred to TGR by the buffer operation will be the write data Figure 17 48 shows the timing in this case Compare match signal Write signal Address Pφ Buffer register address Buffer register TGR write cycle T1 T2 M TGR N M Buffer register write data Figure 17 48 Contention between Buffer Register Write and Compare Match ...

Page 771: ... input capture signal is generated in the T1 state of a TGR read cycle the data that is read will be the data before input capture transfer Figure 17 49 shows the timing in this case Input capture signal Read signal Address Pφ TGR address TGR TGR read cycle T1 T2 N Internal data bus N M Figure 17 49 Contention between TGR Read and Input Capture ...

Page 772: ...input capture signal is generated in the T2 state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 17 50 shows the timing in this case Input capture signal Write signal Address Pφ TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 17 50 Contention between TGR Write and Input Capture ...

Page 773: ... in the T2 state of a buffer register write cycle the buffer operation takes precedence and the write to the buffer register is not performed Figure 17 51 shows the timing in this case Input capture signal Write signal Address Pφ TCNT Buffer register write cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 17 51 Contention between Buffer Register Write and Input Capture ...

Page 774: ...d counter clearing occur simultaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 17 52 shows the operation timing when a TGR compare match is specified as the clearing source and H FFFF is set in TGR Counter clear signal TCNT input clock Pφ TCNT TGF Disabled TCFV H FFFF H 0000 Figure 17 52 Contention between Overflow and Counter Clearing ...

Page 775: ... H FFFF M TCNT write data TCFV flag Disabled Figure 17 53 Contention between TCNT Write and Overflow Multiplexing of I O Pins In the Chip the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with the TIOCD0 I O pin the TCLKC input pin with the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be ...

Page 776: ...2 If clearing when the TPU timer is stopped write 0 to the flag again after executing clearing 17 8 2 DMA Transfer by TPU0 When DMA transfer is performed by means of TPU channel 0 compare match or input capture internal logic interrupt requests transfer requests may not be cleared correctly Therefore it may not be possible to execute DMA transfer when a subsequent transfer request is generated by ...

Page 777: ...tandard Five test signals TCK TDI TDO TMS and TRST TAP controller Instruction register Data register Bypass register Boundary scan register The H UDI has seven instructions Bypass mode Test mode conforming to IEEE 1149 1 EXTEST mode Test mode corresponding to IEEE1149 1 SAMPLE PRELOAD mode Test mode corresponding to IEEE1149 1 CLAMP mode Test mode corresponding to IEEE1149 1 HIGHZ mode Test mode c...

Page 778: ...controller H UDI interrupt signal SDSR SDIDR SDDRH SDDRL Shift register SDBPR Mux TDO Peripheral bus SDIR Instruction register TCK Test clock SDSR Status register TMS Test mode select SDDRH Data register H TRST Test reset SDDRL Data register L TDI Test data input SDBPR Bypass register TDO Test data output SDBSR Boundary scan register SDIDR ID code register Decoder 16 SDIR SDBSR Figure 18 1 H UDI B...

Page 779: ...2 Data register H SDDRH R W Undefined H FFFFFCB4 8 16 32 Data register L SDDRL R W Undefined H FFFFFCB6 8 16 32 Bypass register SDBPR Boundary scan register SDBSR ID code register SDIDR H 0005200F Notes 1 Indicates whether the register can be read written to by the CPU 2 Initial value when the TRST signal is input Registers are not initialized by a reset power on or manual or in standby mode Instr...

Page 780: ...est Clock TCK The test clock pin TCK provides an independent clock supply to the H UDI As the clock input to TCK is supplied directly to the H UDI a clock waveform with a duty cycle close to 50 should be input for details see section 22 Electrical Characteristics If no clock is input TCK is fixed at 1 by internal pull up 18 2 2 Test Mode Select TMS The test mode select pin TMS is sampled on the ri...

Page 781: ... Register SDIR Bit 15 14 13 12 11 10 9 8 TS3 TS2 TS1 TS0 Initial value 1 1 1 0 0 0 0 0 R W R R R R R R R R Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R The instruction register SDIR is a 16 bit register that can only be read by the CPU H UDI instructions can be transferred to SDIR by serial input from TDI SDIR can be initialized by the TRST signal but is not initialized by...

Page 782: ... Bit 12 TS0 Description 0 0 0 0 EXTEST mode 1 Reserved 1 0 CLAMP mode 1 HIGHZ mode 1 0 0 SAMPLE PRELOAD mode 1 Reserved 1 0 Reserved 1 Reserved 1 0 0 0 Reserved 1 Reserved 1 0 H UDI interrupt 1 Reserved 1 0 0 Reserved 1 Reserved 1 0 IDCODE mode Initial value 1 BYPASS mode Bits 11 to 0 Reserved These bits are always read as 0 The write value should always be 0 ...

Page 783: ... In the case of a 2 bit shift the SDTRF bit is first output followed by a reserved bit SDSR is initialized by TRST signal input but is not initialized by a reset or in standby mode Bits 15 to 1 Reserved Bits 15 to 11 and 7 to 1 are always read as 0 and the write value should always be 0 Bits 10 to 8 are always read as 1 and the write value should always be 1 Bit 0 Serial Data Transfer Control Flag...

Page 784: ...is input only the last 32 bits will be stored in SDDR Serial data is input starting from the MSB of SDDR bit 15 of SDDRH and output starting from the LSB bit 0 of SDDRL This register is not initialized by a reset in standby mode or by the TRST signal 18 3 4 Bypass Register SDBPR The bypass register SDBPR is a one bit shift register In bypass mode SDBPR is connected to TDI and TDO and the chip is e...

Page 785: ...Input Output Bit No from TDI 34 D0 Input 329 Output 328 Output enable 327 36 D1 Input 326 Output 325 Output enable 324 37 D2 Input 323 Output 322 Output enable 321 38 D3 Input 320 Output 319 Output enable 318 39 D4 Input 317 Output 316 Output enable 315 40 D5 Input 314 Output 313 Output enable 312 41 D6 Input 311 Output 310 Output enable 309 43 D7 Input 308 Output 307 Output enable 306 44 D8 Input...

Page 786: ...tput 295 Output enable 294 49 D12 Input 293 Output 292 Output enable 291 51 D13 Input 290 Output 289 Output enable 288 53 D14 Input 287 Output 286 Output enable 285 54 D15 Input 284 Output 283 Output enable 282 55 D16 Input 281 Output 280 Output enable 279 56 D17 Input 278 Output 277 Output enable 276 57 D18 Input 275 Output 274 Output enable 273 59 D19 Input 272 Output 271 Output enable 270 ...

Page 787: ...tput 265 Output enable 264 64 D22 Input 263 Output 262 Output enable 261 65 D23 Input 260 Output 259 Output enable 258 68 D24 Input 257 Output 256 Output enable 255 70 D25 Input 254 Output 253 Output enable 252 71 D26 Input 251 Output 250 Output enable 249 72 D27 Input 248 Output 247 Output enable 246 73 D28 Input 245 Output 244 Output enable 243 74 D29 Input 242 Output 241 Output enable 240 ...

Page 788: ...80 A0 Output 233 Output enable 232 82 A1 Output 231 Output enable 230 83 A2 Output 229 Output enable 228 84 A3 Output 227 Output enable 226 85 A4 Output 225 Output enable 224 86 A5 Output 223 Output enable 222 87 A6 Output 221 Output enable 220 88 A7 Output 219 Output enable 218 90 A8 Output 217 Output enable 216 92 A9 Output 215 Output enable 214 93 A10 Output 213 Output enable 212 94 A11 Output ...

Page 789: ...t 203 Output enable 202 100 A16 Output 201 Output enable 200 102 A17 Output 199 Output enable 198 103 A18 Output 197 Output enable 196 104 A19 Output 195 Output enable 194 105 A20 Output 193 Output enable 192 106 A21 Output 191 Output enable 190 107 A22 Output 189 Output enable 188 108 A23 Output 187 Output enable 186 111 A24 Output 185 Output enable 184 115 WAIT Input 183 117 RAS Output 182 Outpu...

Page 790: ... 122 DQMLL WE0 Output 172 Output enable 171 123 CAS3 Output 170 Output enable 169 124 CAS2 Output 168 Output enable 167 125 CAS1 Output 166 Output enable 165 126 CAS0 Output 164 Output enable 163 127 CKE Output 162 Output enable 161 128 RD Output 160 Output enable 159 129 REFOUT Output 158 Output enable 157 131 BS Output 156 Output enable 155 133 RD WR Output 154 Output enable 153 134 CS0 Output 1...

Page 791: ...able 143 139 BUSHIZ Input 142 140 BH Output 141 Output enable 140 141 DREQ1 Input 139 142 DREQ0 Input 138 143 DACK1 Output 137 Output enable 136 144 DACK0 Output 135 Output enable 134 145 BRLS Input 133 148 BGR Output 132 Output enable 131 151 PB15 Input 130 Output 129 Output enable 128 152 PB14 Input 127 Output 126 Output enable 125 153 PB13 Input 124 Output 123 Output enable 122 154 PB12 Input 1...

Page 792: ... Output 114 Output enable 113 159 PB9 Input 112 Output 111 Output enable 110 160 PB8 Input 109 Output 108 Output enable 107 161 PB7 Input 106 Output 105 Output enable 104 162 PB6 Input 103 Output 102 Output enable 101 163 PB5 Input 100 Output 99 Output enable 98 164 PB4 Input 97 Output 96 Output enable 95 165 PB3 Input 94 Output 93 Output enable 92 166 PB2 Input 91 Output 90 Output enable 89 ...

Page 793: ... 85 Output 84 Output enable 83 171 PA13 Input 82 Output 81 Output enable 80 172 PA12 Input 79 Output 78 Output enable 77 173 PA11 Input 76 Output 75 Output enable 74 174 PA10 Input 73 Output 72 Output enable 71 175 PA9 Input 70 Output 69 Output enable 68 176 PA8 Input 67 Output 66 Output enable 65 177 PA7 Input 64 Output 63 Output enable 62 178 PA6 Input 61 Output 60 Output enable 59 ...

Page 794: ... 183 CKPO Output 52 Output enable 51 184 PA2 Input 50 Output 49 Output enable 48 185 PA1 Input 47 Output 46 Output enable 45 186 PA0 Input 44 Output 43 Output enable 42 187 RX ER Input 41 188 RX DV Input 40 189 COL Input 39 190 CRS Input 38 192 RX CLK Input 37 194 ERXD0 Input 36 195 ERXD1 Input 35 196 ERXD2 Input 34 197 ERXD3 Input 33 198 MDIO Input 32 Output 31 Output enable 30 199 MDC Output 29 ...

Page 795: ...t 18 Output enable 17 208 TX ER Output 16 Output enable 15 1 IRL3 Input 14 2 IRL2 Input 13 3 IRL1 Input 12 4 IRL0 Input 11 5 NMI Input 10 13 MD4 Input 9 14 MD3 Input 8 15 MD2 Input 7 16 MD1 Input 6 17 MD0 Input 5 24 CKPREQ CKM Input 4 25 CKPACK Output 3 Output enable 2 27 IVECF Output 1 Output enable 0 to TDO Note The output enable signals are active low When an output enable signal is driven low ...

Page 796: ...R is a 32 bit register In the IDCODE mode SDIDR can output H 0005200F which is a fixed code from TDO However no serial data can be written to SDIDR via TDI For SDIDR read write by the CPU cannot be performed 31 28 27 12 11 1 0 0000 0001 0000 0101 0010 0000 0000 111 1 Version 4 bits Part Number 16 bits Manufacture Identify 11 bits Fixed Code 1 bit ...

Page 797: ...ates of TAP controller State transitions basically conform with the JTAG standard Test logic reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR scan Run test idle 1 0 0 0 0 1 1 1 1 1 1 0 0 1 0 1 1 1 0 Capture IR Shift IR Exit1 IR Pause IR Exit2 IR Update IR Select IR scan 0 0 1 0 0 1 0 1 1 1 0 0 Figure 18 2 TAP Controller State Transitions ...

Page 798: ...rrupt and serial transfer procedure is as follows 1 An instruction is input to SDIR by serial transfer and an H UDI interrupt request is generated 2 After the H UDI interrupt request is issued the SDTRF bit in SDSR is monitored externally After output of SDTRF 1 from TDO is observed serial data is transferred to SDDR 3 On completion of the serial transfer to SDDR the SDTRF bit is cleared to 0 and ...

Page 799: ...DDR access by the CPU or serial transfer data input output to SDDR is possible 1 SDDR is shift disabled SDDR access by the CPU is enabled 2 SDDR is shift enabled Do not access SDDR until SDTRF 0 Conditions SDTRF 1 When TRST 0 When the CPU writes 1 In bypass mode SDTRF 0 End of SDDR shift access in serial transfer 2 SDSR SDDR Update DR state internal MUX switchover timing Switchover from SDSR to SD...

Page 800: ...c Reset Run Test Idle Exit1 DR Update DR TS0 TS3 Exit1 IR SDTRF Figure 18 4 Data Input Output Timing Chart 2 TCK TMS TDI TDO TRST Select DR Select DR Capture DR Shift DR Exit1 DR Update DR Select DR Capture DR Shift DR Update DR Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 SDTRF SDTRF Shift DR Capture DR Shift DR Select DR Update DR Capture DR Update DR Exit1 DR Exit1 DR Exit1 DR Figure 18 ...

Page 801: ...ndary scan register outputs values from the scan path and loads data onto the scan path When this instruction is executing the SH7616 s input pin signals are transmitted directly to the internal circuitry and internal circuit values are directly output externally from the output pins The SH7616 s system circuits are not affected by execution of this instruction The instruction code is 0100 In a SA...

Page 802: ...PLE PRELOAD instruction While the CLAMP instruction is enabled the state of the boundary scan register maintains the previous state regardless of the state of the TAP controller A bypass register is connected between TDI and TDO The related circuit operates in the same way when the BYPASS instruction is enabled The instruction code is 0010 HIGHZ When the HIGHZ instruction is enabled all output pin...

Page 803: ...zed in standby mode If TRST is set to 0 in standby mode bypass mode will be entered The frequency of TCK must be lower than that of the peripheral module clock Pφ For details see section 22 Electrical Characteristics In data transfer data input output starts with the LSB Figure 18 6 shows serial data input output When data that exceeds the number of bits of the register connected between TDI and T...

Page 804: ...R and SDSR serial data input output In Capture IR SDIR and SDSR are captured into the shift register and in Shift IR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO In Update IR data input from TDI is written to SDIR but not to SDSR Capture IR TDI TDI input data TDO Shift register Bit 31 Bit 15 Bit 16 Bit 0 Bit 15 Bit 0 Update IR Figure 18 6 Serial Data Input Output...

Page 805: ...e SDTRF 1 is read from TDO when an H UDI interrupt is generated SDSR and SDIR are captured into the shift register in Capture DR and in Shift DR bits 0 to 15 of SDSR and bits 0 to 15 of SDIR are output in that order from TDO In Update DR TDI input data is not written to any register 2 In H UDI interrupt mode after SDTRF 1 is read from TDO when an H UDI interrupt is generated SDDRH and SDDRL are ca...

Page 806: ...ut In IDCODE mode SDIDR is captured into the shift register in Capture DR and in Shift DR bits 0 to 31 of SDIDR are output in that order from TDO In Update DR data input from TDI is not written to any register TDI SDIDR SDIDR TDO Shift register Bit 31 Bit 15 Bit 0 Bit 0 Capture DR Figure 18 6 Serial Data Input Output 3 ...

Page 807: ...n Controller PFC 19 1 Overview The pin function controller PFC consists of registers to select multiplexed pin functions and input output direction The pin function and input output direction can be selected for individual pins regardless of the operating mode of the chip Table 19 1 shows the chip s multiplex pins ...

Page 808: ... B PB15 I O Port SCK1 I O SCIF1 B PB14 I O Port RXD1 I SCIF1 B PB13 I O Port TXD1 O SCIF1 B PB12 I O Port SRCK2 I SIO2 RTS O SCIF1 STATS1 O BSC B PB11 I O Port SRS2 I SIO2 CTS I SCIF1 STATS0 O BSC B PB10 I O Port SRXD2 I SIO2 TIOCA1 I O TPU1 B PB9 I O Port STCK2 I SIO2 TIOCB1 I O TPU1 B PB8 I O Port STS2 I O SIO2 TIOCA2 I O TPU2 B PB7 I O Port STXD2 O SIO2 TIOCB2 I O TPU2 B PB6 I O Port SRCK1 I SI...

Page 809: ...2 R W H 0000 H FFFFFC8E 8 16 19 3 Register Descriptions 19 3 1 Port A Control Register PACR Bit 15 14 13 12 11 10 9 8 PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PA7MD PA6MD PA5MD PA4MD PA3MD PA2MD PA1MD PA0MD Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W The port A control register PACR is a 16 bit r...

Page 810: ...t PA11MD Selects the function of pin PA11 SRXD0 Bit 11 PA11MD Description 0 General input output PA11 Initial value 1 SIOF serial receive data SRXD0 Bit 10 PA10 Mode Bit PA10MD Selects the function of pin PA10 STCK0 Bit 10 PA10MD Description 0 General input output PA10 Initial value 1 SIOF serial transmit clock STCK0 Bit 9 PA9 Mode Bit PA9MD Selects the function of pin PA9 STS0 Bit 9 PA9MD Descrip...

Page 811: ...itial value 1 FRT clock input FTCI Bit 5 PA5 Mode Bit PA5MD Selects the function of pin PA5 FTI Bit 5 PA5MD Description 0 General input output PA5 Initial value 1 FRT input capture input FTI Bit 4 PA4 Mode Bit PA4MD Selects the function of pin PA4 FTO4 Bit 4 PA4MD Description 0 General input output PA4 Initial value 1 FRT output compare output FTOA Bit 3 PA3 Mode Bit PA3MD Selects the function of ...

Page 812: ...W R W R W Bit 7 6 5 4 3 2 1 0 PA7IOR PA6IOR PA5IOR PA4IOR PA2IOR PA1IOR PA0IOR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R R W R W R W The port A I O register PAIOR is a 16 bit read write register that selects the input output direction of the 14 multiplex pins in port A Bits PA13IOR to PA4IOR and PA2IOR to PA0IOR correspond to individual pins in port A PAIOR is enabled when port A pins fu...

Page 813: ...et They are not initialized by a manual reset or in standby mode or sleep mode Port B Control Register PBCR Bit 15 14 13 12 11 10 9 8 PB15 MD1 PB15 MD0 PB14 MD1 PB14 MD0 PB13 MD1 PB13 MD0 PB12 MD1 PB12 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 PB11 MD1 PB11 MD0 PB10 MD1 PB10 MD0 PB9 MD1 PB9 MD0 PB8 MD1 PB8 MD0 Initial value 0 0 0 0 0 0 0 0 R W R W R ...

Page 814: ...al input output PB13 Initial value 1 Reserved 1 0 SCIF1 serial data output TXD1 1 Reserved Bits 9 and 8 PB12 Mode Bits 1 and 0 PB12MD1 PB12MD0 These bits select the function of pin PB12 SRCK2 RTS STATS1 Bit 9 PB12MD1 Bit 8 PB12MD0 Description 0 0 General input output PB12 Initial value 1 SIO2 serial receive clock input SRCK2 1 0 SCIF1 transmit request RTS 1 BSC status 1 output STATS1 Bits 7 and 6 ...

Page 815: ...on of pin PB9 STCK2 TIOCB1 TCLKC Bit 3 PB9MD1 Bit 2 PB9MD0 Description 0 0 General input output PB9 Initial value 1 SIO2 serial transmit clock input STCK2 1 0 TPU1 input capture input output compare output TIOCB1 1 Reserved Note Timer clock input C TCLKC is selected when the TPU phase counting mode is set or according to the setting of bits TPSC2 to TPSC0 in TCR Bits 1 and 0 PB8 Mode Bits 1 and 0 ...

Page 816: ...7MD0 These bits select the function of pin PB7 STXD2 TIOCB2 TCLKD Bit 15 PB7MD1 Bit 14 PB7MD0 Description 0 0 General input output PB7 Initial value 1 SIO2 serial transmit data output STXD2 1 0 TPU2 input capture input output compare output TIOCB2 1 Reserved Note Timer clock input D TCLKD is selected when the TPU phase counting mode is set or according to the setting of bits TPSC2 to TPSC0 in TCR ...

Page 817: ...al input output PB4 Initial value 1 SIO1 serial receive data input SRXD1 1 0 SCIF2 serial data output TXD2 1 Reserved Bits 7 and 6 PB3 Mode Bits 1 and 0 PB3MD1 PB3MD0 These bits select the function of pin PB3 STCK1 TIOCA0 Bit 7 PB3MD1 Bit 6 PB3MD0 Description 0 0 General input output PB3 Initial value 1 SIO1 serial transmit clock input STCK1 1 0 TPU0 input capture input output compare output TIOCA...

Page 818: ...C0 1 Reserved Note Timer clock input A TCLKA is selected when the TPU phase counting mode is set or according to the setting of bits TPSC2 to TPSC0 in TCR Bits 1 and 0 PB0 Mode Bits 1 and 0 PB0MD1 PB0MD0 These bits select the function of pin PB0 TIOCD0 TCLKB Bit 1 PB0MD1 Bit 0 PB0MD0 Description 0 0 General input output PB0 Initial value 1 Reserved 1 0 TPU0 input capture input output compare outpu...

Page 819: ...W R W R W R W R W R W R W R W The port B I O register PBIOR is a 16 bit read write register that selects the input output direction of the 16 multiplex pins in port B Bits PB15IOR to PB0IOR correspond to individual pins in port B PBIOR is enabled when port B pins function as general input pins PB15 to PB0 and disabled otherwise When port B pins function as PB15 to PB0 a pin becomes an output when ...

Page 820: ...Section 19 Pin Function Controller PFC Rev 2 00 Mar 09 2006 page 794 of 906 REJ09B0292 0200 ...

Page 821: ...output port with the 14 pins shown in figure 20 1 Of the 14 pins the CKPO pin has no port data register bit and is multiplexed as an internal clock pin PA13 input output SRCK0 input PA12 input output SRS0 input PA11 input output SRXD0 input PA10 input output STCK0 input PA9 input output STS0 input output PA8 input output STXD0 output WDTOVF output PA7 input output PA6 input output FTCI input PA5 i...

Page 822: ...DR is a 16 bit read write register that stores port A data Bits 15 14 and 3 are reserved they always read 0 and the write value should always be 0 Bits PA13DR to PA0DR correspond to pins PA13 to PA0 When a pin functions as a general output if a value is written to PADR that value is output directly from the pin and if PADR is read the register value is returned directly regardless of the pin state...

Page 823: ...utput PB12 input output PB11 input output PB10 input output PB9 input output PB8 input output PB7 input output PB6 input output PB5 input output PB4 input output PB3 input output PB2 input output PB1 input output PB0 input output Reserved SCK1 input output Reserved RXD1 input Reserved TXD1 output SRCK2 input RTS output STATS1 output SRS2 input CTS input STATS0 output SRXD2 input TIOCA1 input outpu...

Page 824: ...hat value is output directly from the pin and if PBDR is read the register value is returned directly regardless of the pin state When a pin functions as a general input if PBDR is read the pin state not the register value is returned directly If a value is written to PBDR although that value is written into PBDR it does not affect the pin state Table 20 4 shows port B data register read write ope...

Page 825: ... and the DSP unit a sleep mode which halts CPU functions and a standby mode which halts all functions 21 1 1 Power Down Modes The following modes and function are provided as power down modes 1 Sleep mode 2 Standby mode 3 Module standby function UBC DMAC DSP FRT SCIF1 2 TPU SIOF SIO1 2 Table 21 1 shows the transition conditions for entering the modes from the program execution state as well as the...

Page 826: ...Halted and register values held UBC Halted and register values held Other than UBC Halted Held or high impedance 1 NMI interrupt 2 Power on reset 3 Manual reset Module standby function MSTP bit for relevant module is set to 1 Runs Runs When MSTP is 1 the clock supply is halted Runs When an MSTP bit is 1 the clock supply to the relevant module is halted FRT and SCIF1 2 pins are initialized and othe...

Page 827: ...struction puts the chip into standby mode Bit 6 Port High Impedance HIZ Selects whether output pins are set to high impedance or retain the output state in standby mode When HIZ 0 initial state the specified pin retains its output state When HIZ 1 the pin goes to the high impedance state See Appendix B 1 Pin States during Resets Power Down States and Bus Release State for which pins are controlled...

Page 828: ...clock halts the operation result prior to the halt is retained This bit should be set when the DSP unit is halted When the DSP unit is halted no instructions with a DSP register MACH or MACL as an operand can be used Bit 3 MSTP3 Description 0 DSP running Initial value 1 Clock supply to DSP halted Bit 2 Reserved This bit is always read as 0 The write value should always be 0 Bit 1 Module Stop 1 MST...

Page 829: ... TPU is halted When the clock halts the TPU retains its pre halt state and the TPU interrupt vector register in the INTC retains its pre halt value Therefore when MSTP11 is cleared to 0 and the clock supply to the TPU is resumed the TPU starts operating again Bit 5 MSTP11 Description 0 TPU running Initial value 1 Clock supply to TPU halted Bit 4 Module Stop 10 MSTP10 Specifies halting the clock su...

Page 830: ...d to 0 and the clock supply to SIOF is restarted operation starts again Bit 2 MSTP8 Description 0 SIOF running Initial value 1 Clock supply to SIOF halted Bit 1 Module Stop 7 MSTP7 Specifies halting the clock supply to SCIF2 When the MSTP7 bit is set to 1 the supply of the clock to SCIF2 is halted When the clock halts the SCIF2 registers are initialized but the SCIF2 interrupt vector register in t...

Page 831: ...use its priority level is equal to or less than the mask level set in the CPU s status register SR or if an interrupt by an on chip peripheral module is disabled at the peripheral module Cancellation by a DMA Address Error If a DMA address error occurs sleep mode is canceled and DMA address error exception handling is executed Cancellation by a Power On Reset A power on reset cancels sleep mode Ca...

Page 832: ...DMA request response selection control registers 0 and 1 Vector number setting registers DMA0 and DMA1 Watchdog timer WDT Bits 7 5 of the timer control status register Bits 2 0 of the timer control status register Reset control status register Timer counter 16 bit free running timer FRT All registers Serial communication interface with FIFO SCIF1 2 All registers Serial I O with FIFO SIOF All regis...

Page 833: ...s entered when the clock is halted and goes high on recovering from standby mode when the clock starts after oscillation has stabilized The high level at the NMI pin should be held for at least 3 cycles after the start of clock signal output from the CKIO pin Cancellation by a Power On Reset A power on reset cancels standby mode Cancellation by a Manual Reset A manual reset cancels standby mode 21...

Page 834: ... the timer enable bit TME in the WDT s timer control status register WTCSR is 1 When the clock pause request function is used the standby bit SBY in the standby control register 1 SBYCR1 must be set to 1 before inputting the request signal The clock pause function is used as described below 1 Set the TME bit in the watchdog timer s WTCSR register to 0 and set the SBY bit in SBYCR1 to 1 2 Apply a l...

Page 835: ...al notification that the chip can be operated The standby state all on chip peripheral module states and all pin states during clock pause are the same as in the normal standby mode Figure 21 2 shows the timing chart for the clock pause function CKIO input CKPREQ CKM input CKPACK output Frequency modification Clock pause request cancellation Clock pause acceptance processing WDT count up Normal st...

Page 836: ...lation Clock pause acceptance processing Normal state Clock pause state Figure 21 3 Clock Pause Function Timing Chart PLL Circuit 1 Halted The clock pause state can be canceled by means of NMI input in the same way as the normal standby state The clock pause request should be canceled within four CKIO clock cycles after NMI input Figure 21 4 shows the timing chart for clock pause state cancellatio...

Page 837: ... are not retained in standby mode when cache is used as on chip RAM 2 If an on chip peripheral register is written in the 10 clock cycles before the chip transits to standby mode read the register before executing the SLEEP instruction 3 When using clock mode 0 1 or 2 the CKIO pin is the clock output pin Note the following when standby mode is used in these clock modes When standby mode is cancele...

Page 838: ...dby mode With the module standby function the external pins of the DMAC and SIO0 SIO2 on chip peripheral modules retain their states prior to halting as do DMAC DSP and SIO0 SIO2 registers The external pins of the FRT SCIF1 2 and TPU are reset and all their registers are initialized An on chip peripheral module corresponding to a module standby bit must not be switched to the module standby state ...

Page 839: ...VCC 0 3 to 4 2 V Power supply voltage 5 V I O PVCC 0 3 to 7 0 V Input voltage excluding 5 V I O Vin 0 3 to Vcc 0 3 V Input voltage 5 V I O Vin 0 3 to PVcc 0 3 V Operating temperature Topr 20 to 75 C Storage temperature Tstg 55 to 125 C Notes 1 Permanent damage to the chip may result if the maximum ratings are exceeded 2 When powering on turn on the 5 V I O power supply PVCC after or at the same ti...

Page 840: ... Other input pins VCC 0 7 VCC 0 3 V Input low voltage RES NMI MD4 to MD0 TRST CKPREQ CKM VIL 0 3 VCC 0 1 V Other input pins 0 3 0 8 V Schmitt trigger PB14 RXD1 PB5 SRS1 RXD2 VT 0 8 V input voltage VT 4 0 V PVCC 5 V 0 5 V VT 2 6 V Other than above VT VT 0 3 V Input leakage current All input pins lin 1 0 µA Vin 0 5 to VCC 0 5 V Vin 0 5 to PVCC 0 5 V Three state leakage current All I O and output pin...

Page 841: ... 6 V CPU operating clock 62 5 MHz peripheral modules not used Standby mode 990 µA Note Do not leave the PLLVcc and PLLVss pins open when the PLL circuit is not used Connect the PLLVcc pin to Vcc and the PLLVss pin to Vss Table 22 3 Permissible Output Currents Conditions VCC PLLVCC 3 3 V 0 3 V PVCC 5 0 V 0 5 V 3 3 V 0 3 V PVCC VCC VSS PVSS PLLVSS 0 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Permi...

Page 842: ...p time and hold times for each input signal are observed Table 22 4 Maximum Operating Frequencies Conditions VCC PLLVCC 3 3 V 0 3 V PVCC 5 0 V 0 5 V 3 3 V 0 3 V PVCC VCC VSS PVSS PLLVSS 0 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Notes Operating CPU DSP f 1 62 5 MHz tIcyc frequency External bus SDRAM not used 1 31 25 tEcyc External bus SDRAM used 1 62 5 tEcyc Peripheral modules 1 31 25 tPcyc ...

Page 843: ...dth tCKIL 8 3 12 4 ns CKIO clock input high level pulse width tCKIH 8 3 12 4 ns CKIO clock input rise time tCKIR 4 ns CKIO clock input fall time tCKIF 4 ns CKIO clock output frequency fOP 1 5 8 6 62 5 MHz 22 3 CKIO clock output cycle time tcyc 16 1000 5 125 6 ns CKIO clock output low level pulse width tCKOL 3 ns CKIO clock output high level pulse width tCKOH 3 ns CKIO clock rise time tCKOR 5 ns CK...

Page 844: ...VCC 1 2 VCC VIL VIL EXTAL input Note When clock is input from EXTAL pin Figure 22 1 EXTAL Clock Input Timing tCKIH tCKIF tCKIR tCKIL tCKIcyc VIH 1 2 VCC 1 2 VCC VIH VIL VIH VIL CKIO input Figure 22 2 CKIO Clock Input Timing tcyc tCKOL tCKOH VOH 1 2VCC CKIO output 1 2VCC tCKOR tCKOF VOH VOL VOL VOH Figure 22 3 CKIO Clock Output Timing ...

Page 845: ... Oscillation stabilization time when using on chip crystal oscillator Figure 22 4 Power On Oscillation Stabilization Time at Power On CKIO internal clock Stable oscillation Standby tOSC2 tRESW RES Note Oscillation stabilization time when using on chip crystal oscillator Figure 22 5 Oscillation Stabilization Time after Standby Recovery Recovery by RES RES RES RES ...

Page 846: ...Note Oscillation stabilization time when using on chip crystal oscillator Figure 22 6 Oscillation Stabilization Time after Standby Recovery Recovery by NMI tPLL EXTAL or CKIO Stable oscillation Stable oscillation Change of oscillation frequency PLL synchronization PLL synchronization Internal clock Figure 22 7 PLL Synchronization Stabilization Time ...

Page 847: ... setup time tRESS 3tEcyc 40 ns 22 9 NMI setup time tNMIS 40 ns IRL3 IRL0 setup time tIRLS 30 ns NMI hold time tNMIH 20 ns IRL3 IRL0 hold time tIRLH 20 ns BRLS setup time tBLSS 10 ns 22 10 BRLS hold time tBLSH 5 ns BGR delay time tBGRD 15 ns Bus tri state delay time tBOFF 0 35 ns Bus buffer on time tBON 0 35 ns Note The RES NMI and IRL3 IRL0 signals are asynchronous inputs If the setup times shown ...

Page 848: ...0200 tRESS CKIO RES tNMIS NMI tIRLS IRL3 IRL0 tNMIH tIRLH VIH VIL VIH VIL VIH VIL Figure 22 9 Interrupt Signal Input Timing A24 A0 D31 D0 RD RD WR RAS CAS CSn WEn BS IVECF BRLS input BGR output tBLSS CKIO tBOFF tBON tBON tBOFF tBGRD tBGRD tBLSH tBLSS tBLSH Figure 22 10 Bus Release Timing ...

Page 849: ...o 34 39 42 to 44 Read strobe delay time 1 tRSD1 14 ns 22 11 12 15 16 22 30 33 34 37 39 40 42 to 44 Read data setup time 1 tRDS1 8 ns 22 11 33 37 42 to 44 Read data setup time 2 EDO tRDS2 8 ns 22 39 40 Read data setup time 3 SDRAM tRDS3 6 5 ns 22 15 16 Read data hold time 2 tRDH2 0 ns 22 11 42 Read data hold time 4 SDRAM tRDH4 2 ns 22 15 16 Read data hold time 5 DRAM tRDH5 0 ns 22 33 37 Read data h...

Page 850: ... tRASD1 1 14 ns 22 15 to 18 20 to 25 28 to 32 RAS delay time 2 DRAM EDO tRASD2 14 ns 22 33 34 39 41 RAS delay time 3 EDO tRASD3 14 ns 22 39 CAS delay time 1 SDRAM tCASD1 1 14 ns 22 15 16 17 18 22 to 28 30 to 32 42 CAS delay time 2 DRAM tCASD2 14 ns 22 33 34 37 to 41 DQM delay time tDQMD 1 14 ns 22 15 16 18 to 20 22 24 to 29 CKE delay time tCKED 1 14 ns 22 32 OE delay time 1 tOED1 14 ns 22 39 OE de...

Page 851: ...elay time 2 Eø Iø 1 1 tWDD2 9 5 ns 22 25 27 Write data hold time 1 tWDH1 2 ns 22 25 27 Address delay time tAD 4 11 ns 22 15 16 18 20 22 24 25 26 27 28 30 31 32 CS delay time 1 tCSD1 2 5 9 5 ns 22 15 16 18 20 22 23 24 25 28 30 31 32 Read write delay time tRWD 2 5 9 5 ns 22 15 16 18 20 21 22 24 25 28 29 30 31 32 DQM delay time tDQMD 2 5 9 5 ns 22 15 16 18 19 20 22 24 25 26 27 28 29 RAS delay time 1 ...

Page 852: ...WEn DQMxx RAS CAS OE CKE DACKn 2 WAIT A24 A0 T1 T2 tAD tAS tBSD tBSD tAD tCSD1 tRWD tRWD tWED1 tRDS1 tRDH2 1 tWED1 tCSD2 tRSD1 tRSD1 tDACD1 tDACD2 D31 D0 Notes 1 tRDH2 is measured from the rise of CSn or RD whichever comes first 2 DACKn waveform when active high is specified Figure 22 11 Basic Read Cycle No Wait ...

Page 853: ...9B0292 0200 CKIO BS CSn RD WR RD WEn DQMxx RAS CAS OE CKE D31 D0 DACKn WAIT A24 A0 T1 T2 tAD tBSD tBSD tAD tCSD1 tRWD tRWD tRSD1 tRSD1 tCSD2 tWED1 tWED1 tDACD1 tDACD2 tDON tWDH1 tWDD1 tDOF Note DACKn waveform when active high is specified tAS Figure 22 12 Basic Write Cycle No Wait ...

Page 854: ...cs Rev 2 00 Mar 09 2006 page 828 of 906 REJ09B0292 0200 T1 Tw T2 CKIO BS CSn RD WR RD WEn DQMxx RAS CAS OE CKE D31 D0 DACKn WAIT A24 A0 tWTH tWTS Note DACKn waveform when active high is specified Figure 22 13 Basic Bus Cycle 1 Wait Cycle ...

Page 855: ... Mar 09 2006 page 829 of 906 REJ09B0292 0200 T1 Tw Twx T2 CKIO BS CSn RD WR RD WEn DQMxx RAS CAS OE CKE D31 D0 DACKn WAIT A24 A0 tWTS tWTH tWTS tWTH Note DACKn waveform when active high is specified Figure 22 14 Basic Bus Cycle External Wait Input ...

Page 856: ...tCASD1 tCASD1 tDQMD tRASD1 tDACD1 tCASD1 tCASD1 1 tRDH4 tRWD tRSD1 tCSD1 tAD tBSD Notes 1 Dotted line shows the case where synchronous DRAM in a different CS space is accessed 2 DACKn waveform when active high is specified CKIO BS CSn RD WR RD WEn DQMxx D31 D0 RAS CAS OE CKE DACKn 2 WAIT Address upper bits Address lower bits Figure 22 15 Synchronous DRAM Read Bus Cycle RCD 1 Cycle CAS Latency 1 Cy...

Page 857: ...D Notes 1 Dotted line shows the case where synchronous DRAM in a different CS space is accessed 2 DACKn waveform when active high is specified CKIO BS CSn RD WR RD WEn DQMxx RAS CAS OE CKE D31 D0 WAIT Address upper bits Address lower bits DACKn 2 tCASD1 tCASD1 tRASD1 tDQMD tRSD1 tRWD tCSD1 tBSD tAD 1 Figure 22 16 Synchronous DRAM Single Read Bus Cycle RCD 1 Cycle CAS Latency 1 Cycle Burst 4 ...

Page 858: ...0 1 DACKn 2 WAIT Tr Trw Tc Tw Td1 Td2 Td3 Td4 TdE tRASD1 tCASD1 tCASD1 tRASD1 Address upper bits Address lower bits Notes 1 Dotted line shows the case where synchronous DRAM in a different CS space is accessed 2 DACKn waveform when active high is specified Figure 22 17 Synchronous DRAM Read Bus Cycle RCD 2 Cycles CAS Latency 2 Cycles Burst 4 ...

Page 859: ...4 Tde tAD tBSD tRWD tCSD1 tDQMD tDACD1 tCASD1 tCASD1 tCASD1 tCASD1 tRASD1 CKIO BS CSn RD WR RD WEn DQMxx CAS CKE D31 D0 DACKn WAIT RAS Address upper bits Address lower bits Note DACKn waveform when active high is specified Figure 22 18 Synchronous DRAM Read Bus Cycle Bank Active Same Row Access CAS Latency 1 Cycle ...

Page 860: ...92 0200 TC TW Td1 Td2 Td3 Td4 Tde tDQMD Address upper bits Address lower bits BS CKIO CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE Note DACKn waveform when active high is specified Figure 22 19 Synchronous DRAM Read Bus Cycle Bank Active Same Row Access CAS Latency 2 Cycles ...

Page 861: ...tAD tRWD tRWD tDACD1 tRASD1 tRASD1 tDQMD tCSD1 tBSD Address upper bits Address lower bits BS CKIO CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE Note DACKn waveform when active high is specified Figure 22 20 Synchronous DRAM Read Bus Cycle Bank Active Different Row Access TRP 1 Cycle RCD 1 Cycle CAS Latency 1 Cycle ...

Page 862: ...er bits Address lower bits BS CKIO Tp Tpw Tr Tc Td1 Tde CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tRWD tRASD1 tRASD1 Note DACKn waveform when active high is specified Figure 22 21 Synchronous DRAM Read Bus Cycle Bank Active Different Row Access TRP 2 Cycles RCD 1 Cycle CAS Latency 1 Cycle ...

Page 863: ...S OE CKE tAD tAD tAD tBSD tCSD1 tRWD tDQMD tDACD1 tRASD1 tRASD1 tCASD1 tCASD1 tCASD1 tRASD1 tRASD1 tDQMD tDOF tDACD1 tDACD1 tDON tWDD1 tRWD tRWD tRSD1 tCSD1 tCSD1 tBSD tWDH1 Notes 1 Dotted line shows the case where synchronous DRAM in a different CS space is accessed 2 DACKn waveform when active high is specified 1 1 1 Figure 22 22 Synchronous DRAM Write Bus Cycle RASD 0 RCD 1 Cycle TRWL 1 Cycle ...

Page 864: ...s Address lower bits BS CSn RD WR RD WEn DQMxx D31 D0 DACKn 2 WAIT RAS CAS OE CKE tRASD1 tCASD1 tRASD1 tCSD1 Notes 1 Dotted line shows the case where synchronous DRAM in a different CS space is accessed 2 DACKn waveform when active high is specified 1 1 Figure 22 23 Synchronous DRAM Write Bus Cycle RASD 0 RCD 2 Cycles TRWL 2 Cycles ...

Page 865: ...r bits BS CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tAD tAD tBSD tBSD tCSD1 tCSD1 tRWD tRWD tDQMD tDQMD tWDD1 tDOF tWDH1 tDON tDACD1 tDACD1 tRASD1 tCASD1 tCASD1 Note DACKn waveform when active high is specified Figure 22 24 Synchronous DRAM Write Bus Cycle Bank Active Same Row Access Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 866: ...ess lower bits BS CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tAD tAD tBSD tBSD tCSD1 tCSD1 tRWD tRWD tDQMD tDQMD tWDD2 tDOF tWDH1 tDON tDACD1 tDACD1 tRASD1 tCASD1 tCASD1 Note DACKn waveform when active high is specified Figure 22 25 Synchronous DRAM Write Cycle Bank Active Same Row Access Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 867: ... Address upper bits Address lower bits BS CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tAD Tc tDQMD tWDD1 tWDH1 tCASD1 tCASD1 Note DACKn waveform when active high is specified Figure 22 26 Synchronous DRAM Continuous Write Cycle Bank Active Same Row Access Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 868: ... CKIO Address upper bits Address lower bits BS CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tAD Tc tDQMD tWDD2 tWDH1 tCASD1 tCASD1 Note DACKn waveform when active high is specified Figure 22 27 Synchronous DRAM Continuous Write Cycle Bank Active Same Row Access Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 869: ...pper bits Address lower bits BS CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tAD Tp Tr Tc tBSD tCSD1 tRWD tRWD tDQMD tDQMD tDACD1 tRASD1 tCASD1 Note DACKn waveform when active high is specified Figure 22 28 Synchronous DRAM Write Bus Cycle Bank Active Different Row Access TRP 1 Cycle RCD 1 Cycle ...

Page 870: ...ress upper bits Address lower bits BS CKIO Tp Tpw Tr Trw Tc CSn RD WR RD WEn DQMxx D31 D0 DACKn WAIT RAS CAS OE CKE tRWD tDQMD tRASD1 tRASD1 Note DACKn waveform when active high is specified Figure 22 29 Synchronous DRAM Write Bus Cycle Bank Active Different Row Access TRP 2 Cycles RCD 2 Cycles ...

Page 871: ...WAIT Address upper bits Trr Trc1 Tre Trc2 Address lower bits tRASD1 tRSD1 tRASD1 tCASD1 tCASD1 tAD tAD tCSD1 tRWD tRWD tBSD tCSD1 Note An auto refresh cycle is always preceded by a precharge cycle The number of cycles between the two is determined by the number of cycles specified by TRP Figure 22 30 Synchronous DRAM Auto Refresh Cycle TRAS 4 Cycles ...

Page 872: ...09B0292 0200 CKIO BS RD CSn RD WR WEn DQMxx RAS CAS OE D31 D0 DACKn WAIT Address upper bits Tp Trr Trc2 Tre Trc1 Address lower bits CKE tRASD1 tCASD1 tAD tAD tBSD tCSD1 tRWD tRWD Figure 22 31 Synchronous DRAM Auto Refresh Cycle Shown from Precharge Cycle TRP 1 Cycle TRAS 4 Cycles ...

Page 873: ...re Trc1 CSn RD WR WEn DQMxx D31 D0 DACKn RD WAIT RAS CAS OE CKE tAD tRWD tAD tRASD1 tCASD1 tCKED tCKED tRASD1 tCSD1 tCSD1 Tre tRASD1 tCASD1 Note A self refresh cycle is always preceded by a precharge cycle The number of cycles between the two is determined by the number of cycles specified by TRP Figure 22 32 Synchronous DRAM Self Refresh Cycle TRAS 3 ...

Page 874: ...ASxx RAS CAS OE CKE D31 D0 DACKn 2 WAIT Address upper bits Address lower bits tRSD1 tCASD2 tCSD2 tCSD1 tRWD tRWD tRASD2 tRASD2 tDACD1 tRSD1 tRDH5 1 tCASD2 tRASD2 Notes 1 tRDH5 is measured from the rise of RD or CASxx whichever comes first 2 DACKn waveform when active high is specified tRSD1 tCASD2 tASC Figure 22 33 DRAM Read Cycle TRP 1 Cycle RCD 1 Cycle No Wait ...

Page 875: ...ACD2 tAD BS CSn RD WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT Address upper bits Address lower bits tCASD2 tCSD2 tCSD1 tRWD tRWD tRASD2 tRASD2 tRASD2 tRSD1 tDON tWDH1 tDOF tCASD2 tCASD2 tWDD1 tASC tDS tDACD1 Note DACKn waveform when active high is specified tASR Figure 22 34 DRAM Write Cycle TRP 1 Cycle RCD 1 Cycle No Wait ...

Page 876: ...0 of 906 REJ09B0292 0200 CKIO BS CSn RD WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT Address upper bits Address lower bits Tp Tpw Tr Trw Tc1 Tc2 Tw tWTH tWTS Note DACKn waveform when active high is specified Figure 22 35 DRAM Bus Cycle TRP 2 Cycles RCD 2 Cycles 1 Wait ...

Page 877: ...REJ09B0292 0200 CKIO Tp Tr Tc1 Tw Twx Tc2 BS CSn RD WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT Address upper bits Address lower bits tWTS tWTH tWTS tWTH Note DACKn waveform when active high is specified Figure 22 36 DRAM Bus Cycle TRP 1 Cycle RCD 1 Cycle External Wait Input ...

Page 878: ... CASxx RAS CAS OE CKE D31 D0 DACKn 2 WAIT Address upper bits Address lower bits tRSD1 tRSD1 tCASD2 tASC tASC tCASD2 tDACD2 tRDS1 CSn tRDH5 1 tRDS1 tRDH5 1 Notes 1 tRDH5 is measured from the rise of RD or CASxx whichever comes first 2 DACKn waveform when active high is specified Figure 22 37 DRAM Burst Read Cycle TRP 1 Cycle RCD 1 Cycle No Wait ...

Page 879: ...KIO Tp Tr Tc1 Tc2 Tc1 Tc2 tAD tDACD1 BS CSn RD WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT Address upper bits Address lower bits tWDH1 tCASD2 tWDD1 tDACD2 Note DACKn waveform when active high is specified tCASD2 tASC tDS tDS Figure 22 38 DRAM Burst Write Cycle TRP 1 Cycle RCD 1 Cycle No Wait ...

Page 880: ...E CKE D31 D0 DACKn 1 WAIT Address upper bits Address lower bits tRSD1 tASC tCSD2 tCSD1 tRWD tRWD tCASD2 tRASD3 tRASD2 tRASD2 tOED2 tOED1 tOED1 tRDH6 tRSD1 Notes 1 DACKn waveform when active high is specified 2 tRDH7 is measured from the rise of RAS or CAS OE whichever comes first tRSD1 tCASD2 tDACD1 tASR tAD tCASD2 Figure 22 39 EDO Read Cycle TRP 1 Cycle RCD 1 Cycle No Wait ...

Page 881: ...Tr Tc1 Tc2 Tc1 Tc2 tAD tDACD1 BS RD WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT Address upper bits Address lower bits tRSD1 tRSD1 tCASD2 tCASD2 tASC tDACD2 tRDS2 CSn tRDH6 tRDH6 tRDS2 Note DACKn waveform when active high is specified Figure 22 40 EDO Burst Read Cycle TRP 1 Cycle RCD 1 Cycle No Wait ...

Page 882: ...9B0292 0200 CKIO BS CSn RD WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT Address upper bits Address lower bits Tp tCSD1 Trr Trc1 Trc2 Tre tCASD2 tCASD2 tCASD2 tRASD2 tRASD2 tRASD2 tCSD1 Figure 22 41 DRAM CAS CAS CAS CAS Before RAS RAS RAS RAS Refresh Cycle TRP 1 Cycle TRAS 2 Cycles ...

Page 883: ...WR RD CASxx RAS CAS OE CKE D31 D0 DACKn WAIT T1 TW T2 TW T2 tAD tBSD tCSD1 tRWD tRSD1 tRWD tBSD tBSD tBSD tAD tAD tCSD2 tRSD1 tRDH2 tRDS1 tWTS tWTH tWTS tWTH tDACD1 tDACD1 tDACD2 tDACD2 tRDS1 tRDH2 tCASD1 tCASD1 tRSD1 tRSD1 Note DACKn waveform when active high is specified Figure 22 42 Burst ROM Read Cycle Wait 1 ...

Page 884: ...2 00 Mar 09 2006 page 858 of 906 REJ09B0292 0200 T1 T2 T3 T4 tAD tAD tRWD tBSD tBSD tIVD tRSD1 tRSD1 tRSD1 CKIO A3 A0 IVECF RD WR RD D7 D0 BS tIVD tRWD tRDH8 WAIT tWTS tWTH Figure 22 43 Interrupt Vector Fetch Cycle No Wait Iφ φ φ φ Eφ φ φ φ 1 1 ...

Page 885: ...2 00 Mar 09 2006 page 859 of 906 REJ09B0292 0200 T1 T2 tAD tAD tIVD tRWD tBSD tBSD tIVD tRSD1 tRSD1 tRSD1 CKIO A3 A0 IVECF RD WR RD D7 D0 BS tRDH8 WAIT tWTS tWTH Figure 22 44 Interrupt Vector Fetch Cycle No Wait Iφ φ φ φ Eφ φ φ φ other than 1 1 ...

Page 886: ...09 2006 page 860 of 906 REJ09B0292 0200 CKIO A3 A0 RD WR WAIT D7 D0 RD IVECF T1 TW T2 tWTH tWTS tWTH tWTS BS Figure 22 45 Interrupt Vector Fetch Cycle External Wait Input Iφ φ φ φ Eφ φ φ φ other than 1 1 tREFOD CKIO REFOUT Figure 22 46 REFOUT Delay Time ...

Page 887: ...ming Table 22 8 Direct Memory Access Controller Timing Conditions VCC PLLVCC 3 3 V 0 3 V PVCC 5 0 V 0 5 V 3 3 V 0 3 V PVCC VCC VSS PVSS PLLVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure DREQ0 DREQ1 setup time tDRQS 10 ns 22 47 DREQ0 DREQ1 hold time tDRQH 5 ns tDRQH tDRQS CKIO DREQ0 DREQ1 Figure 22 47 DREQ0 DREQ1 Input Timing ...

Page 888: ... Input capture input setup time tEcyc tPcyc 1 2 tFICS tcyc 50 ns 22 49 Input capture input setup time tEcyc tPcyc 1 4 tFICS 3tcyc 50 ns 22 49 Input capture input hold time tFICH 50 ns 22 48 22 49 Timer clock input setup time tEcyc tPcyc 1 1 tFCKS 50 ns 22 50 Timer clock input setup time tEcyc tPcyc 1 2 tFCKS tcyc 50 ns 22 51 Timer clock input setup time tEcyc tPcyc 1 4 tFCKS 3tcyc 50 ns 22 51 Time...

Page 889: ...292 0200 FTOA FTOB FTI CKIO tFICS tFICH tFOCD Figure 22 49 FRT Input Output Timing tEcyc tPcyc other than 1 1 CKIO FTCI tFCKWL tFCKWH tFCKS Figure 22 50 FRT Clock Input Timing tEcyc tPcyc 1 1 CKIO FTCI tFCKWL tFCKWH tFCKS Figure 22 51 FRT Clock Input Timing tEcyc tPcyc other than 1 1 ...

Page 890: ...Unit Figure Input clock cycle tscyc 4 tPcyc 22 52 Input clock cycle synchronous mode tscyc 6 tPcyc 22 53 Input clock pulse width tSCKW 0 4 0 6 tcscyc 22 52 Transmit data delay time synchronous mode tTXD 100 ns 22 53 Receive data setup time synchronous mode tRXS 100 ns Receive data hold time synchronous mode tRXH 100 ns RTS delay time tRTSD 100 ns 22 54 CTS setup time synchronous mode tCTSS 100 ns ...

Page 891: ...2006 page 865 of 906 REJ09B0292 0200 tscyc tTXD tRXS tRXH SCK TxD transmit data RxD receive data Figure 22 53 SCI Input Output Timing Synchronous Mode tscyc tRTSD tCTSS tCTSH SCK1 RTS CTS Figure 22 54 RTS RTS RTS RTS and CTS CTS CTS CTS Input Output Timing ...

Page 892: ... Timer input setup time tEcyc tPcyc 1 2 tTICS tcyc 50 ns 22 55 22 56 Timer input setup time tEcyc tPcyc 1 4 tTICS 3tcyc 50 ns Timer clock input setup time tEcyc tPcyc 1 1 tTCKS 50 ns 22 57 Timer clock input setup time tEcyc tPcyc 1 2 tTCKS tcyc 50 ns Timer clock input setup time tEcyc tPcyc 1 4 tTCKS 3tcyc 50 ns Timer clock pulse width Single edge specified tTCKWH 1 5 tcyc Both edges specified tTC...

Page 893: ...f 906 REJ09B0292 0200 tTOCD tTICS CKIO Output compare output Input capture input Note TIOCA0 TIOCA2 TIOCB0 TIOCB2 TIOCC0 TIOCD0 Figure 22 56 TPU Input Output Timing tEcyc tPcyc other than 1 1 tTCKS tTCKS tTCKWL tTCKWH CKIO TCLKA TCLKD Figure 22 57 TPU Clock Input Timing ...

Page 894: ... Conditions VCC PLLVCC 3 3 V 0 3 V PVCC 5 0 V 0 5 V 3 3 V 0 3 V PVCC VCC VSS PVSS PLLVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure WDTOVF delay time tWOVD 70 ns 22 58 22 59 CKIO WDTOVF tWOVD tWOVD Figure 22 58 Watchdog Timer Output Timing tEcyc tPcyc 1 1 CKIO WDTOVF tWOVD tWOVD Figure 22 59 Watchdog Timer Output Timing tEcyc tPcyc other than 1 1 ...

Page 895: ... SRCK0 STCK0 clock input low level width tSFWL 0 4 tSFcyc ns SRCKn STCKn clock input low level width n 1 or 2 tWL 0 4 tSIcyc ns SRCK0 STCK0 clock input high level width tSFWH 0 4 tSFcyc ns SRCKn STCKn clock input high level width n 1 or 2 tWH 0 4 tSIcyc ns SRS input setup time tRSS 15 ns 22 61 SRS input hold time tRSH 10 ns SRXD input setup time tSRDS 15 ns SRXD input hold time tSRDH 10 ns STS0 in...

Page 896: ...006 page 870 of 906 REJ09B0292 0200 tSFWH tSFWL tSFcyc STCK0 SRCK0 STCKn SRCKn n 1 or 2 SIOF SIO tWH tWL tSIcyc Figure 22 60 SIOF SIO Input Clock Timing SRCKn input SRSn input SRXDn input n 0 1 or 2 tSRDS tSRDH tRSS tRSH Figure 22 61 SIOF SIO Receive Timing ...

Page 897: ...CK0 input SIOF STS0 input STXD0 output tTDD tTDD tSFTSS tTSH STCKn input SIO STSn input STXDn output n 1 or 2 tTDD tTDD tTSS tTSH Figure 22 62 SIOF SIO Transmit Timing TMn 0 Mode STCKn input STSn output STXDn output n 0 1 or 2 tTDD tTDD tTSD tTSD Figure 22 63 SIOF SIO Transmit Timing TMn 1 Mode ...

Page 898: ...time ttcyc tPcyc or 66 7 ns ns 22 64 TCK clock input high level width tTCKH 0 4 0 6 ttcyc TCK clock input low level width tTCKL 0 4 0 6 ttcyc TRST pulse width tTRSW 20 ttcyc 22 65 TRST setup time tTRSS 40 ns TMS setup time tTMSS 30 ns 22 66 TMS hold time tTMSH 10 ns TDI setup time tTDIS 30 ns TDI hold time tTDIH 10 ns TDO delay time tTDOD 0 30 ns Note Specified as tPcyc or 66 7 whichever is greate...

Page 899: ...Timing Conditions VCC PLLVCC 3 3 V 0 3 V PVCC 5 0 V 0 5 V 3 3 V 0 3 V PVCC VCC VSS PVSS PLLVSS 0 V Ta 20 to 75 C Item Symbol Min Max Unit Figure Port output data delay time tPWD 50 ns 22 67 22 68 Port input data setup time tEcyc tPcyc 1 1 tPRS 50 ns 22 67 Port input data setup time tEcyc tPcyc 1 2 tPRS tcyc 50 ns 22 68 Port input data setup time tEcyc tPcyc 1 4 tPRS 3tcyc 50 ns Port input data hol...

Page 900: ...f 906 REJ09B0292 0200 CKIO PA0 PA13 PB0 PB15 read PA0 PA13 PB0 PB15 write tPWD tPRS tPRH Figure 22 67 I O Port Input Output Timing tEcyc tPcyc 1 1 CKIO PA0 PA13 PB0 PB15 read PA0 PA13 PB0 PB15 write tPWD tPRS tPRH Figure 22 68 I O Port Input Output Timing tEcyc tPcyc 1 1 ...

Page 901: ...CRSs 10 ns CRS hold time tCRSh 10 ns COL setup time tCOLs 10 ns 22 70 COL hold time tCOLh 10 ns RX CLK cycle time tRcyc 2 4 tcyc 22 71 RX DV setup time tRDVs 10 ns RX DV hold time tRDVh 3 ns ERXD 3 0 setup time tERDs 10 ns ERXD 3 0 hold time tERDh 3 ns RX ER setup time tRERs 10 ns 22 72 RX ER hold time tRERh 3 ns MDIO setup time tMDIOs 10 ns 22 73 MDIO hold time tMDIOh 10 ns MDIO output data hold ...

Page 902: ...TX EN ETXD 3 0 TX ER CRS COL tCRSs tETDd Preamble Figure 22 69 MII Send Timing Normal Operation Preamble JAM TX CLK TX EN ETXD 3 0 TX ER CRS COL tCOLh tCOLs Figure 22 70 MII Send Timing Case of Conflict tRDVs SFD DATA CRC RX CLK RX DV ERXD 3 0 RX ER tERDs tERDh tRDVh Preamble Figure 22 71 MII Receive Timing Normal Operation ...

Page 903: ...XXXX RX CLK RX DV ERXD 3 0 RX ER tRERs tRERh Preamble Figure 22 72 MII Receive Timing Case of Error MDC tMDIOs tMDIOh MDIO Figure 22 73 MDIO Input Timing MDC tMDIOdh MDIO Figure 22 74 MDIO Output Timing RX CLK tWOLd WOL Figure 22 75 WOL Output Timing CKIO tEXOUTd EXOUT Figure 22 76 EXOUT Output Timing ...

Page 904: ...ignal Timing Conditions VCC PLLVCC 3 3 V 0 3 V PVCC 5 0 V 0 5 V 3 3 V 0 3 V PVCC VCC VSS PVSS PLLVSS 0 V Ta 20 to 75 C Item Symbol Min Typ Max Unit Figure STAS1 and STAS0 output delay time tSTATd 16 ns 22 77 BH output rising edge delay time tBHNrd 16 ns 22 78 BH output falling edge delay time tBHNfd 16 ns BUSHiZ setup time tBHIZs 7 ns 22 79 BUSHiZ hold time tBHIZh 8 ns Output delay time of target ...

Page 905: ...00 CPU CPU G DMAC G DMAC G DMAC G DMAC G DMAC G DMAC G DMAC G DMAC CKI0 Address BH tBHNfd tBHNrd Read0 Read1 Read2 Read3 Write0 Write1 Write2 Write3 Figure 22 79 BH BH BH BH Output Timing CKI0 tBHIZs tBHIZh tBHIZd WAIT BUSHiZ Target Pins Figure 22 80 BUSHiZ BUSHiZ BUSHiZ BUSHiZ Bus Timing ...

Page 906: ... RES TRST EXTAL CKIO MD0 MD4 and NMI Input rise fall time 1 ns The output load circuit is shown in figure 22 81 IOL CL SH7616 output pin DUT output VREF IOH CL is the total value including the capacitance of the test jig etc The capacitance of each pin is as follows 30 pF CKIO A24 A0 D31 D0 BS RD CS4 CS0 DQMUU WE3 DQMLL WE0 CAS3 CAS0 RAS CAS OE DACK1 DACK0 50 pF All other pins IOL and IOH values a...

Page 907: ...Bit 2 Bit 1 Bit 0 Module H FFFFFC00 SIRDR SIOF H FFFFFC01 H FFFFFC02 SITDR H FFFFFC03 H FFFFFC04 SICTR DMACE TCIE RCIE H FFFFFC05 TM SE DL TIE RIE TE RE H FFFFFC06 SISTR TCD RCD H FFFFFC07 TERR RERR TDRE RDRF H FFFFFC08 SIFCR TRMD LM RFRST TFRST H FFFFFC09 RFWM3 RFWM2 RFWM1 RFWM0 TFWM3 TFWM2 TFWM1 TFWM0 H FFFFFC0A SIFDR R4 R3 R2 R1 R0 H FFFFFC0B T4 T3 T2 T1 T0 H FFFFFC0C SIRCDR H FFFFFC0D H FFFFFC...

Page 908: ...TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU H FFFFFC51 TMDR0 BFB BFA MD3 MD2 MD1 MD0 H FFFFFC52 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FFFFFC53 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H FFFFFC54 TIER0 TCIEV TGIED TGIEC TGIEB TGIEA H FFFFFC55 TSR0 TCFV TGFD TGFC TGFB TGFA H FFFFFC56 TCNT0 H FFFFFC57 H FFFFFC58 TGR0A H FFFFFC59 H FFFFFC5A TGR0B H FFFFFC5B H FFFFFC5C TGR...

Page 909: ...FFFFFC78 TGR2A H FFFFFC79 H FFFFFC7A TGR2B H FFFFFC7B H FFFFFC7C to H FFFFFC7F H FFFFFC80 PACR PA13MD PA12MD PA11MD PA10MD PA9MD PA8MD PFC H FFFFFC81 PA7MD PA6MD PA5MD PA4MD PA3MD PA2MD PA1MD PA0MD H FFFFFC82 PAIOR PA13IOR PA12IOR PA11IOR PA10IOR PA9IOR PA8IOR H FFFFFC83 PA7IOR PA6IOR PA5IOR PA4IOR PA2IOR PA1IOR PA0IOR H FFFFFC84 PADR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR I O port H FFFFFC85 PA7...

Page 910: ...DIR TS3 TS2 TS1 TS0 H UDI H FFFFF CB1 H FFFFF CB2 SDSR H FFFFF CB3 SDTRF H FFFFF CB4 SDDRH H FFFFF CB5 H FFFFF CB6 SDDRL H FFFFF CB7 H FFFFF CB8 to H FFFFF CBF H FFFF FCC0 SCBRR1 C A CHR ICK 3 PE ICK1 O E ICK1 STOP ICK0 MP CKS1 CKS0 SCIF1 H FFFF FCC1 H FFFF FCC2 SCBRR1 H FFFF FCC3 H FFFF FCC4 SCSCR1 TIE RIE TE RE MPIE CKE1 CKE0 H FFFF FCC5 H FFFF FCC6 SCFTDR1 H FFFF FCC7 H FFFF FCC8 SC1SSR1 PER3 P...

Page 911: ...2 H FFFF FCE1 H FFFF FCE2 SCBRR2 H FFFF FCE3 H FFFF FCE4 SCSCR2 TIE RIE TE RE MPIE CKE1 CKE0 H FFFF FCE5 H FFFF FCE6 SCFTDR2 H FFFF FCE7 H FFFF FCE8 SC1SSR2 PER3 PER2 PER1 PER0 FER3 FER2 FER1 FER0 H FFFF FCE9 ER TEND TDFE BRK FER PER RDF DR H FFFF FCEA SC2SSR2 TLM RLM N1 N0 MPB MPBT EI ORER H FFFF FCEB H FFFF FCEC SCFRDR2 H FFFF FCED H FFFF FCEE SCFCR2 RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP ...

Page 912: ...8 H FFFF FD0F TDLA7 TDLA6 TDLA5 TDLA4 TDLA3 TDLA2 TDLA1 TDLA0 H FFFF FD10 RDLAR RDLA31 RDLA30 RDLA29 RDLA28 RDLA27 RDLA26 RDLA25 RDLA24 H FFFF FD11 RDLA23 RDLA22 RDLA21 RDLA20 RDLA19 RDLA18 RDLA17 RDLA16 H FFFF FD12 RDLA15 RDLA14 RDLA13 RDLA12 RDLA11 RDLA10 RDLA9 RDLA8 H FFFF FD13 RDLA7 RDLA6 RDLA5 RDLA4 RDLA3 RDLA2 RDLA1 RDLA0 H FFFF FD14 EESR RFCOF H FFFF FD15 ECI TC TDE TFUF FR RDE RFOF H FFFF ...

Page 913: ... FD2B RFD2 RFD1 RFD0 H FFFF FD2C RCR H FFFF FD2D H FFFF FD2E H FFFF FD2F RNC H FFFF FD30 EDOCR H FFFF FD31 H FFFF FD32 H FFFF FD33 FEC AEC EDH H FFFF FD34 to H FFFF FD3F H FFFF FD40 RBWAR RBWA31 RBWA30 RBWA29 RBWA28 RBWA27 RBWA26 RBWA25 RBWA24 H FFFF FD41 RBWA23 RBWA22 RBWA21 RBWA20 RBWA19 RBWA18 RBWA17 RBWA16 H FFFF FD42 RBWA15 RBWA14 RBWA13 RBWA12 RBWA11 RBWA10 RBWA9 RBWA8 H FFFF FD43 RBWA7 RBWA...

Page 914: ... TDFA25 TDFA24 H FFFF FD51 TDFA23 TDFA22 TDFA21 TDFA20 TDFA19 TDFA18 TDFA17 TDFA16 H FFFF FD52 TDFA15 TDFA14 TDFA13 TDFA12 TDFA11 TDFA10 TDFA9 TDFA8 H FFFF FD53 TDFA7 TDFA6 TDFA5 TDFA4 TDFA3 TDFA2 TDFA1 TDFA0 H FFFF FD54 to H FFFF FD5F H FFFF FD60 ECMR EtherC H FFFF FD61 H FFFF FD62 PRCEF MPDE H FFFF FD63 RE TE ILB ELB DM PRM H FFFF FD64 ECSR H FFFF FD65 H FFFF FD66 H FFFF FD67 LCHNG MPD ICD H FFF...

Page 915: ...ROC15 TROC14 TROC13 TROC12 TROC11 TROC10 TROC9 TROC8 H FFFF FD83 TROC7 TROC6 TROC5 TROC4 TROC3 TROC2 TROC1 TROC0 H FFFF FD84 CDCR H FFFF FD85 H FFFF FD86 COLDC15 COLDC14 COLDC13 COLDC12 COLDC11 COLDC10 COLDC9 COLDC8 H FFFF FD87 COLDC7 COLDC6 COLDC5 COLDC4 COLDC3 COLDC2 COLDC1 COLDC0 H FFFF FD88 LCCR H FFFF FD89 H FFFF FD8A LCC15 LCC14 LCC13 LCC12 LCC11 LCC10 LCC9 LCC8 H FFFF FD8B LCC7 LCC6 LCC5 LC...

Page 916: ...SFC4 TSFC3 TSFC2 TSFC1 TSFC0 H FFFF FDA0 TLFRCR H FFFF FDA1 H FFFF FDA2 TLFC15 TLFC14 TLFC13 TLFC12 TLFC11 TLFC10 TLFC9 TLFC8 H FFFF FDA3 TLFC7 TLFC6 TLFC5 TLFC4 TLFC3 TLFC2 TLFC1 TLFC0 H FFFF FDA4 RFCR H FFFF FDA5 H FFFF FDA6 RFC15 RFC14 RFC13 RFC12 RFC11 RFC10 RFC9 RFC8 H FFFF FDA7 RFC7 RFC6 RFC5 RFC4 RFC3 RFC2 RFC1 RFC0 H FFFF FDA8 MAFCR H FFFF FDA9 H FFFF FDAA MAFC15 MAFC14 MAFC13 MAFC12 MAFC1...

Page 917: ...G0BV2 TG0BV1 TG0BV0 H FFFFFE44 VCRF TG0CV6 TG0CV5 TG0CV4 TG0CV3 TG0CV2 TG0CV1 TG0CV0 H FFFFFE45 TG0DV6 TG0DV5 TG0DV4 TG0DV3 TG0DV2 TG0DV1 TG0DV0 H FFFFFE46 VCRG TC0VV6 TC0VV5 TC0VV4 TC0VV3 TC0VV2 TC0VV1 TC0VV0 H FFFFFE47 H FFFFFE48 VCRH TG1AV6 TG1AV5 TG1AV4 TG1AV3 TG1AV2 TG1AV1 TG1AV0 H FFFFFE49 TG1BV6 TG1BV5 TG1BV4 TG1BV3 TG1BV2 TG1BV1 TG1BV0 H FFFFFE4A VCRI TC1VV6 TC1VV5 TC1VV4 TC1VV3 TC1VV2 TC1...

Page 918: ...NV6 EINV5 EINV4 EINV3 EINV2 EINV1 EINV0 H FFFFFE63 H FFFFFE64 VCRB H FFFFFE65 H FFFFFE66 VCRC FICV6 FICV5 FICV4 FICV3 FICV2 FICV1 FICV0 H FFFFFE67 FOCV6 FOCV5 FOCV4 FOCV3 FOCV2 FOCV1 FOCV0 H FFFFFE68 VCRD FOVV6 FOVV5 FOVV4 FOVV3 FOVV2 FOVV1 FOVV0 H FFFFFE69 H FFFFFE6A to H FFFFFE70 H FFFFFE71 DRCR0 RS4 RS3 RS2 RS1 RS0 DMAC H FFFFFE72 DRCR1 RS4 RS3 RS2 RS1 RS0 H FFFFFE73 to H FFFFFE7F H FFFFFE80 WT...

Page 919: ...A VCRT RER2V6 RER2V5 RER2V4 RER2V3 RER2V2 RER2V1 RER2V0 H FFFFFECB TER2V6 TER2V5 TER2V4 TER2V3 TER2V2 TER2V1 TER2V0 H FFFFFECC VCRU RDF2V6 RDF2V5 RDF2V4 RDF2V3 RDF2V2 RDF2V1 RDF2V0 H FFFFFECD TDE2V6 TDE2V5 TDE2V4 TDE2V3 TDE2V2 TDE2V1 TDE2V0 H FFFFFECE to H FFFFFEDF H FFFFFEE0 ICR NMIL NMIE INTC H FFFFFEE1 EXIMD VECMD H FFFFFEE2 IPRA DMACIP3 DMACIP2 DMACIP1 DMACIP0 H FFFFFEE3 WDTIP3 WDTIP2 WDTIP1 W...

Page 920: ...6 H FFFF FF16 BRSRL BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 H FFFF FF17 BSA7 BSA6 BSA5 BSA4 BSA3 BSA2 BSA1 BSA0 H FFFF FF18 BRDRH BDA31 BDA30 BDA29 DA28 BDA27 BDA26 BDA25 BDA24 H FFFF FF19 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 H FFFF FF1A BRDRL BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 H FFFF FF1B BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0 H FFFF FF1C to H FFFF FF1F H FFFF FF20 BA...

Page 921: ...F45 BAMC23 BAMC22 BAMC21 BAMC20 BAMC19 BAMC18 BAMC17 BAMC16 H FFFFFF46 BAMRCL BAMC15 BAMC14 BAMC13 BAMC12 BAMC11 BAMC10 BAMC9 BAMC8 H FFFFFF47 BAMC7 BAMC6 BAMC5 BAMC4 BAMC3 BAMC2 BAMC1 BAMC0 H FFFFFF48 BBRC H FFFFFF49 CPC1 CPC0 IDC1 IDC0 RWC1 RWC0 SZC1 SZC0 H FFFFFF4A to H FFFFFF4F H FFFF FF50 BDRCH BDC31 BDC30 BDC29 BDC28 BDC27 BDC26 BDC25 BDC24 UBC H FFFF FF51 BDC23 BDC22 BDC21 BDC20 BDC19 BDC18...

Page 922: ... BAMD3 BAMD2 BAMD1 BAMD0 H FFFF FF68 BBRD XYED XYSD H FFFF FF69 CPD1 CPD0 IDD1 IDD0 RWD1 RWD0 SZD1 SZD0 H FFFF FF6A to H FFFF FF6F H FFFF FF70 BDRDH BDD31 BDD30 BDD29 BDD28 BDD27 BDD26 BDD25 BDD24 UBC H FFFF FF71 BDD23 BDD22 BDD21 BDD20 BDD19 BDD18 BDD17 BDD16 H FFFF FF72 BDRDL BDD15 BDD14 BDD13 BDD12 BDD11 BDD10 BDD9 BDD8 H FFFF FF73 BDD7 BDD6 BDD5 BDD4 BDD3 BDD2 BDD1 BDD0 H FFFF FF74 BDMRDH BDMD...

Page 923: ...M H FFFFFF8F AL DS DL TB TA IE TE DE H FFFFFF90 SAR1 H FFFFFF91 H FFFFFF92 H FFFFFF93 H FFFFFF94 DAR1 H FFFFFF95 H FFFFFF96 H FFFFFF97 H FFFFFF98 TCR1 H FFFFFF99 H FFFFFF9A H FFFFFF9B H FFFFFF9C CHCR1 H FFFFFF9D H FFFFFF9E DM1 DM0 SM1 SM0 TS1 TS0 AR AM H FFFFFF9F AL DS DL TB TA IE TE DE H FFFFFFA0 VCRDMA0 H FFFFFFA1 H FFFFFFA2 H FFFFFFA3 VC7 VC6 VC5 VC4 VC3 VC2 VC1 VC0 H FFFFFFA4 to H FFFFFFA7 H F...

Page 924: ...1 A3SHW0 A2SHW1 A2SHW0 A1SHW1 A1SHW0 A0SHW1 A0SHW0 H FFFFFFC6 to H FFFFFFDF H FFFFFFE0 BCR1 A4LW1 A4LW0 A2ENDIA N BSTROM AHLW1 AHLW0 BSC H FFFFFFE1 A1LW1 A1LW0 A0LW1 A0LW0 A4ENDIA N DRAM2 DRAM1 DRAM0 H FFFFFFE2 to H FFFFFFE3 H FFFFFFE4 BCR2 A4SZ1 A4SZ0 BSC H FFFFFFE5 A3SZ1 A3SZ0 A2SZ1 A2SZ0 A1SZ1 A1SZ0 H FFFFFFE6 to H FFFFFFE7 H FFFFFFE8 WCR1 IW31 IW30 IW21 IW20 IW11 IW10 IW01 IW00 BSC H FFFFFFE9 ...

Page 925: ...mes Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module H FFFFFFF2 to H FFFFFFF3 H FFFFFFF4 RTCNT BSC H FFFFFFF5 H FFFFFFF6 to H FFFFFFF7 H FFFFFFF8 RTCOR BSC H FFFFFFF9 H FFFFFFFA to H FFFFFFFB H FFFFFFFC BCR3 A4LW2 AHLW2 A1LW2 A0LW2 BSC H FFFFFFFD DSWW1 DSWW0 BASEL EDO BWE H FFFFFFFE to H FFFFFFFF ...

Page 926: ...ased State Bus control A24 A0 O O Z Z Z O Z D31 D0 Z IO Z Z Z IO Z CS4 CS0 H O Z H H H Z RD WR H O Z H H H Z RAS H O Z H H H Z CAS OE H O Z H H H Z WAIT Z I Z Z Z I Ignored BS H O Z H H H Z RD H O Z H H H Z BGR H O O H H O O BRLS Z I I Z Z I I CKE H O H O O O H DQMUU WE3 H O Z H H H Z DQMUL WE2 H O Z H H H Z DQMLU WE1 H O Z H H H Z DQMLL WE0 H O Z H H H Z REFOUT L O O L Z O O CAS3 CAS0 H O Z H H H...

Page 927: ...IO I IO I peripheral PB13 TXD1 Z IO Z IO Z K Z IO O IO O module PB12 SRCK2 RTS STATS1 Z IO Z Z O IO Z Z O K K K O Z IO I O O IO I O O PB11 SRS2 CTS STATS0 Z IO Z Z O IO Z Z O K K K O Z IO I I O IO I I O PB10 SRXD2 TIOCA1 Z IO Z Z IO Z Z K K K Z IO I IO IO I IO PB9 STCK2 TIOCB1 TCLKC Z IO Z Z IO Z Z K K K Z IO I IO IO I IO PB8 STS2 TIOCA2 Z IO Z Z IO Z Z K K K Z IO IO IO IO IO IO PB7 STXD2 TIOCB2 T...

Page 928: ... IO Z IO Z K K Z IO I IO I PA11 SRXD0 Z IO Z IO Z K K Z IO I IO I PA10 STCK0 Z IO Z IO Z K K Z IO I IO I PA9 STS0 Z IO Z IO Z K K Z IO IO IO IO PA8 STXD0 Z IO Z IO Z K K Z IO O IO O WDTOVF PA7 H H IO H IO O K O Z O IO O IO PA6 FTCI Z IO Z IO Z K Z IO I IO I PA5 FTI Z IO Z IO Z K Z IO I IO I PA4 FTOA Z IO L IO L K Z IO O IO O CKPO FTOB H H L H L K Z O O O O PA2 LNKSTA Z IO I IO I K Z IO I IO I PA1 ...

Page 929: ...I I I COL I I I I I I I MDC O O O O O O O MDIO IO IO IO IO IO IO IO RX CLK I I I I I I I RX DV I I I I I I I RX ER I I I I I I I ERXD ERXD0 I I I I I I I I Input O Output H High level output L Low level output Z High impedance state K Input pins are in the high impedance state output pins maintain their previous state Notes In sleep mode if the DMAC is operating the address data bus and bus contro...

Page 930: ...ineup Rev 2 00 Mar 09 2006 page 904 of 906 REJ09B0292 0200 Appendix C Product Lineup Table C 1 SH7616 Product Lineup Abbreviation Voltage Operating Frequency Mark Code Package SH7616 3 3 V 62 5 MHz HD6417616SF PLQP0208KA A ...

Page 931: ...53 52 157 156 104 105 Z Z D H E H b 2 1 1 Detail F c L A A A L Terminal cross section p 1 1 c b b c 1 25 1 25 0 08 0 08 0 5 8 0 29 8 30 0 30 2 0 15 0 20 1 70 0 15 0 10 0 05 0 27 0 22 0 17 0 22 0 17 0 12 D L1 ZE ZD y x c b1 bp A HD A2 E A1 c1 e e L HE 0 6 0 5 0 4 Max Nom Min Dimension in Millimeters Symbol Reference 28 1 40 30 2 30 0 29 8 1 0 28 θ θ P LQFP208 28x28 0 50 2 7g MASS Typ FP 208C FP 208...

Page 932: ...Appendix D Package Dimensions Rev 2 00 Mar 09 2006 page 906 of 906 REJ09B0292 0200 ...

Page 933: ...1st Edition November 2001 Rev 2 00 March 09 2006 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2006 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 934: ...8 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65...

Page 935: ...SH7616 Hardware Manual ...

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