Renesas SH7616, Hardware Manual

Page: 779 / 935

Section 18 User Debug Interface (H-UDI)
Rev. 2.00 Mar 09, 2006 page 753 of 906
REJ09B0292-0200
18.1.3 Pin Configuration
Table 18.1 shows the H-UDI pin configuration.
Table 18.1 Pin Configuration
Pin Name Abbreviation I/O Function
Test clock TCK Input Test clock input
Test mode select TMS Input Test mode select input signal
Test data input TDI Input Serial data input
Test data output TDO Output Serial data output
Test reset
TRST
Input Test reset input signal
18.1.4 Register Configuration
Table 18.2 shows the H-UDI registers.
Table 18.2 Register Configuration
Register Abbreviation R/W
* 1
Initial Value
* 2
Address
Access Size
(Bits)
Instruction register SDIR R H'E000 H'FFFFFCB0 8/16/32
Status register SDSR R/W H'0701 H'FFFFFCB2 8/16/32
Data register H SDDRH R/W Undefined H'FFFFFCB4 8/16/32
Data register L SDDRL R/W Undefined H'FFFFFCB6 8/16/32
Bypass register SDBPR — — — —
Boundary scan
register SDBSR — — — —
ID code register SDIDR — H'0005200F — —
Notes: 1. Indicates whether the register can be read/written to by the CPU.
2. Initial value when the
TRST
signal is input. Registers are not initialized by a reset
(power-on or manual) or in standby mode.
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and
SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a 1-bit
register to which TDI and TDO are connected in bypass mode. The boundary scan register
(SDBSR) is a 330-bit register, and is connected to TDI and TDO in the SAMPLE/PRELOAD or
EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via