R&S SMJ100A, Operating Manual

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Instrument Function
R&S
®
SMJ100A
318 Operating Manual 1403.7458.32 ─ 14
In modulation modes with fewer than 10bits/symbol, the parallel data is output LSB-jus-
tified. In the case of 8-PSK modulation for example (3bits/symbol) only data lines D0,
D1 and D2 are used.
In the following example, the diagram shows the output signals of an 8-PSK modula-
tion (3 bits per symbol) on the serial DATA interface. The positive edge of the clock is
always used when outputting data. The data source is a data list with 15 bits = 001 010
100 101 110 (5 symbols).
Figure 5-18: Output signal on the serial data interface and clock output signals on the AUX I/O inter-
face
There is a maximum data rate above which serial data processing becomes impossi-
ble. This data rate can be found in the data sheet. If the rate is exceeded the DATA
connector becomes high-impedance, and the output on the CLOCK connector is the
symbol clock instead of the bit clock.
In the following example, the diagram shows the output signals of an 8-PSK modula-
tion (3 bits per symbol) on the parallel interface. The data source is a data list with 15
bits = 001 010 100 101 110 (5 symbols).
Figure 5-19: Data and clock output signals on the parallel AUX I/O interface
In order for parallel external data to be retrieved correctly the rising edge of the symbol
clock must be used, since the timing between the falling edge of the symbol clock and
the data switch on the parallel interface is undefined.
Internal Clock and External Synchronous Data
External serial data
When serial data for "Custom Digital Modulation" is being fed in via the DATA connec-
tor on the front panel, the symbol clock acts as a scanning pulse (strobe) so as to mark
the least significant bit in a symbol.
The clock signals are output on the CLOCK and CLOCK OUT connectors (front panel
and rear panel respectively, choice of bit clock or symbol clock on the latter) and on the
BITCLK or SYMBCLK pins on the AUX I/O interface. Optimum timing is achieved from
using the output signal on the CLOCK connector on the front panel. The setup and
hold times (see following diagram, tsetup and thold) that must be maintained in the
Baseband Signal - Baseband Block