10.5.2.1 ADC Early Interrupt to CLA Response
The ADC can be configured to generate an early interrupt pulse before the ADC conversion completes. If this
option is used to start a CLA task, the CLA will be able to read the result as soon as the conversion result
is available in the ADC result register. This combination of just-in-time sampling along with the low interrupt
response of the CLA enable faster system response and higher frequency control loops. The CLA task trigger to
first instruction fetch interrupt latency is 4 cycles.
Timings for ADC conversions are shown in the timing diagrams of the ADC chapter. If the ADCCLK is a divided
down version of the SYSCLK, the user will have to account for the conversion time in SYSCLK cycles.
For example, if using the ADC with ADCCLK at SYSCLK / 2, it would take 13 ADCCLK x 2 SYSCLK = 26
SYSCLK cycles to complete a conversion.
From a CLA perspective, the pipeline activity is shown in
for an N-cycle (SYSCLK) ADC conversion.
The N-2 instruction will arrive in the R2 phase just in time to read the result register. While the prior instructions
will enter the R2 phase of the pipeline too soon to read the conversion, they can be efficiently used for
pre-processing calculations needed by the task.
Table 10-3. ADC to CLA Early Interrupt Response
ADC Activity
CLA Activity
F1
F2
D1
D2
R1
R2
E
W
Sample
Sample
...
Sample
Conversion
(Cycle 1)
Interrupt Received
Conversion
(Cycle 2)
Task Startup
Conversion
(Cycle 3)
Task Startup
Conversion
(Cycle 4)
I
(Cycle 4)
I
(Cycle 4)
Conversion
(Cycle 5)
I
(Cycle 5)
I
(Cycle 5)
I
(Cycle 4)
Conversion
(...)
...
...
...
...
...
...
...
Conversion
(Cycle N-6)
I
(Cycle N-6)
I
(Cycle N-6)
I
(Cycle N-7)
I
(Cycle N-8)
I
(Cycle N-9)
I
(Cycle N-10)
I
(Cycle N-11)
Conversion
(Cycle N-5)
I
(Cycle N-5)
I
(Cycle N-5)
I
(Cycle N-6)
I
(Cycle N-7)
I
(Cycle N-8)
I
(Cycle N-9)
I
(Cycle N-10)
Conversion
(Cycle N-4)
I
(Cycle N-4)
I
(Cycle N-4)
I
(Cycle N-5)
I
(Cycle N-6)
I
(Cycle N-7)
I
(Cycle N-8)
I
(Cycle N-9)
Conversion
(Cycle N-3)
I
(Cycle N-3)
I
(Cycle N-3)
I
(Cycle N-4)
I
(Cycle N-5)
I
(Cycle N-6)
I
(Cycle N-7)
I
(Cycle N-8)
Conversion
(Cycle N-2)
Read RESULT
Read
RESULT
I
(Cycle N-3)
I
(Cycle N-4)
I
(Cycle N-5)
I
(Cycle N-6)
I
(Cycle N-7)
Conversion
(Cycle N-1)
Read
RESULT
I
(Cycle N-3)
I
(Cycle N-4)
I
(Cycle N-5)
I
(Cycle N-6)
Conversion
(Cycle N-0)
Read
RESULT
I
(Cycle N-3)
I
(Cycle N-4)
I
(Cycle N-5)
Conversion Complete
Read
RESULT
I
(Cycle N-3)
I
(Cycle N-4)
RESULT Latched
Read
RESULT
I
(Cycle N-3)
RESULT Available
Read
RESULT
Control Law Accelerator (CLA)
586
TMS320x2806x Microcontrollers
SPRUH18I – JANUARY 2011 – REVISED JUNE 2022
Copyright © 2022 Texas Instruments Incorporated
Содержание TMS320 2806 Series
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