Individual Functions
6-
123
n
PID
Control
Block
The
following diagram shows the PID control block in the Inverter.
Fig 6.76 PID Control Block
Option Card
Serial Com
Terminal A1
D1-01
D1-02
D1-16
Terminal 16 or 14 PID
target value
RS-422A/485 communications
register 06 H PID target value
Frequency reference
terminal A2 PID feedback
Frequency reference
using multi-step command
PID input volume
(U1-36)
Set PID target value in
multi-function analog input
Set bit 1 of
register 0FH to 1
Proportional
gain (P)
b5-02
Pulse input terminal RP
Pulse input terminal RP
Select multi-function inputs
PID input characteristics
PID SFS Cancel
Output frequency
PID output
gain (b5-10)
Frequency reference
(U1-01)
PID command (U1-38)
Integral (I) time
Store integral using
multi-function inputs
Derivative
time
Integral rset using
multi-function inputs
PID limit
b5-06
PID primary delay
time constant
PID offset
adjustment (b5-07)
Select PID output
characteristics selection
(b5-09)
PID output monitor
(U1-37)
Multi-function input PID control cancel
signal is ON. PID is OFF under the
following conditions:
b5-01 = 0
During JDG command input
Enable/disable reverse operation
when PI output is negative
Upper limit
Lower limit 0
Uppwer limit
Lower limit
Integral
time limit b5-04
Summary of Contents for SYSDRIVE 3G3RV
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