IBM CPC700, User Manual

Page: 38 / 268

3-2 Processor Interface
NOTE: W.B.=Write Buffer; R.B.=Read Buffer
Figure 3. Processor Interface Detailed Block Diagram
3.3 Processor Interface Registers
Processor interface registers are accessed through an indirect method employing a configuration address
register, PIFCFGADR, and a configuration data register, PIFCFGDATA. To access one of the processor
interface registers, write the appropriate index to register PIFCFGADR, then read the data from or write the
data to register PIFCFGDATA. All configuration accesses from the processor must be 4 Byte aligned, oth-
erwise an error will be generated and the cycle not performed.
Table 3. Processor Interface Register Addressing
Table 4 lists the offsets for the various configuration registers located within the processor interface.
Register Address R/W Description
PIFCFGADR FF50_0000 R/W Processor Interface Configuration Address Register
PIFCFGDATA FF50_0004 R/W Processor Interface Configuration Data Register
Table 4. Offsets for Processor Interface Registers
Register Offset R/W Description
PRIFOPT1 00 R/W Processor Interface Options 1
ERRDET1 04 R/W Error Detection 1
ERREN1 08 R/W Error Detection Enable 1
CPUERAD 0C R Processor Error Address
CPUERAT 10 R Processor Error Attributes
Reserved 14
PLBMIFOPT 18 R/W Processor-PLB Master Interface Options
PLBMTLSA1 20 R/W Processor-PLB Master Byte Swap Region 1 Starting Address
Processor Bus
PLB Master
I/F
MC
Processor Interface
PLB
W.B.
DCR Slave
DCR
Master
Mem
W.B.
PLB Master
Interface
PLB Slave
Interface
R.B.
R.B. W.B.
DCR Bus
Bus
PLB Slave
Bus
Arbiter/
Central
Snooper
To
Memory Controller
CONFIG Regs