IBM CPC700, User Manual

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1-8 CPC700 User’s Manual—Preliminary
• Programmable timing per bank.
• Shared address/data/control with SDRAM interface.
• External latch control for shared address bus support.
• Programmable address mapping.
• Peripheral Device pacing with external “Ready”.
ECC
The CPC700 generates, checks, and corrects ECC bits on their way to and from the memory controller.
Write cycles to memory that are less than a word in width require the ECC controller to generate a read
cycle to fetch the appropriate word, modify that word, generate the ECC bits, and write the word back out
to memory.
The ECC controller implements a 64-bit, single-error-correct, double-error-detect, over data and address.
ECC data is 8 bits wide.
• Corrects single-bit data errors.
• Detects double-bit data errors.
• Detects single-bit address errors.
• Detects concurrent single-bit address and single-bit data errors.
• Detects any errors within an aligned nibble.
• Eight check bits support 32- or 64-bit data bus widths.
• Support for mixing ECC and non-ECC DIMMs in the same system.
• ECC checking may be disabled.
UART
The CPC700 contains two UARTs that provide two wire, full duplex serial interfaces to support communi-
cations with serial peripheral devices. Each UART is compatible with the NS 16550 and includes a 16-byte
send and a 16-byte receive FIFO. Features of the UART include:
• Compatible with the NS 16550.
• 16-byte send FIFO, 16-byte receive FIFO.
• Full duplex operation.
• Programmable baud rate generator.
• Supports 5- to 8-bit word size, 1/2 stop bits, even/odd/no parity.
• Two wire transmit/receive external interface.
The UARTs perform serial-to-parallel conversion on data characters received from a peripheral device and
parallel-to-serial conversion on data characters received from the processor. The processor can read the
complete status of the UARTs at any time during the functional operation. Status information reported
includes the type and condition of the transfer operations being performed by the UARTs, as well as any
error conditions, such as parity, overrun, framing and break interrupt.