IBM CPC700, User Manual

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14-6 Register Summary
14.1.6 OPB Bridge Macro Registers
14.1.7 Universal Interrupt Controller Registers
The following table lists the UIC registers. See Section 10.5, “Universal Interrupt Controller Registers” for
detailed register information.
14.1.8 IIC0 Registers
The following table lists the IIC0 registers. See Section 8.4, “IIC Register Definitions” for detailed register
information.
Table 110. OPB Macro Configuration Registers
Register Address R/W Description
GESR FF50_0810 R OPB Bridge Error Status Register (Read/Clear)
GEAR FF50_0818 R OPB Bridge Error Address Register
Table 111. UIC Configuration Registers
Register Address R/W Description
UICSR FF50_0880 R/C UIC Status Register (Read/Clear)
UICSRS FF50_0884 R/S UIC Status Register (Set)
UICER FF50_0888 R/W UIC Enable Register
UICCR FF50_088C R/W UIC Critical Register
UICPR FF50_0890 R/W UIC Polarity Register
UICTR FF50_0894 R/W UIC Trigger Register
UICMSR FF50_0898 R UIC Masked Status Register
UICVR FF50_089C R UIC Vector Register
UICVCR FF50_08A0 W UIC Vector Configuration Register
Table 112. IIC0 Configuration Registers
Register Address R/W Description
IIC0MDBUF FF62_0000 R/W IIC0 Master Data Buffer
Reserved FF62_0001
IIC0SDBUF FF62_0002 R/W IIC0 Slave Data Buffer
Reserved FF62_0003
IIC0LMADR FF62_0004 R/W IIC0 Low Master Address
IIC0HMADR FF62_0005 R/W IIC0 High Master Address
IIC0CNTL FF62_0006 R/W IIC0 Control
IIC0MDCNTL FF62_0007 R/W IIC0 Mode Control