IBM CPC700, User Manual

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5-14 PCI Interface
This command is generated in response to a PLB 1-4 byte write to address FED0_0000h.
As PCI target the CPC700 accepts Memory Write and Invalidate (MWI) on incoming transactions. But as
PCI master it never initiates Memory Write and Invalidate (MWI) transactions. All PCI memory writes are
performed with Memory Writes. As a master the CPC700 never generates a Memory Read Line.
The PCI interface supports PLB size encodings of 1 to 4 bytes. Line and burst sizes are not supported. The
PCI interface posts all writes which decode to PCI memory and PCI I/O space. Posted data is kept in inter-
nal write buffers until it can be transferred to the PCI bus. All other writes and all reads are connected, i.e.
they complete on the PCI bus before completing on the PLB.
5.7.2 PLB Slave Read Handling
PLB master read requests are decoded into four types - PCI Memory, I/O, Configuration and Interrupt
Acknowledge. If the request falls within any of these ranges, and is a supported command type, the bridge
claims the cycle initially by asserting Sl[x]_wait (as opposed to Sl[x]_AddrAck). The bridge must first gain
access to the PCI bus before acknowledging a PLB read request. The specific timing of Sl[x]_AddrAck is
dependent upon the type of transfer.
If the PCI cycle Master Aborts then all beats of read data are returned as 1’s.
5.7.2.1 PLB Reads and Prefetching
When the PCI interface receives PLB 1-4 byte read requests that decode to a PMM marked as non-
prefetchable, The PCI interface runs a single beat read to the PCI as a connected tenure. If the PCI cycle
is retried, the PLB cycle is rearbitrated.
When the PCI interface receives PLB 1-4 byte read requests that decode to a PMM marked as prefetch-
able, the PCI interface burst reads up to 64 bytes from the PCI and saves the data in the PCI Master Read
Prefetch Buffer. Less than 64 bytes may be read if the PCI target disconnects or if the PCI interface’s mas-
ter disconnects due to a Master Latency timeout. Note that the PCI interface’s prefetching is unaffected by
memory management page boundaries (PLB_Guarded is ignored). If a subsequent PLB 1-4 byte read is
contained in the prefetch buffer, then the data is returned to the PLB directly from the prefetch buffer, and
no cycle is generated on the PCI.
If a PLB read to the PCI interface occurs while the PCI interface is prefetching and does not hit in the
prefetch buffer, then the PLB read is rearbitrated. After prefetching completes, any PLB cycle (of any type
or address range) to the PCI interface that does not hit in the prefetch buffer causes the prefetch buffer to
be emptied, and a new PCI read to begin.
5.7.2.2 PLB Reads to the PCI interface’s Configuration Registers
PLB master reads to the PCI interface’s Configuration registers are allowed to execute regardless of
whether or not any write data is posted in the bridge. The Configuration registers are described in Section
5.9 “Bridge Configuration” .
5.7.3 PLB Slave Write Handling (PLB to PCI)
PLB master write requests are decoded into four types - PCI Memory (one of three PMM ranges), PCI I/O,
PCI Configuration, or Special Cycles. If the request falls within any of these ranges, and is a supported
command type, the bridge claims the cycle by asserting Sl[x]_wait. If the write is connected, i.e. translates
to a PCI Configuration or Special Cycle, the bridge must gain access to the PCI bus and successfully