IBM CPC700, User Manual

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14-4 Register Summary
The PCI Interface configuration registers that are accessed through an indirect method employing an
address register, PCICFGADR, and a data register, PCICFGDATA are listed in Table 107. To access one of
the PCI Interface configuration registers, write the appropriate index to register PCICFGADR, then read
the data from or write the data to register PCICFGDATA. See Section 5.9.2, “PCI Configuration Register
and Cycles”, and Section 5.9.3, “PCI Interface Configuration Registers” for important information regarding
these registers.
PTM1MS FF40_0030 R/W PTM 1 Memory Size
PTM1LA FF40_0034 R/W PTM 1 Local Address
PTM2MS FF40_0038 R/W PTM2 Memory Size
PTM2LA FF40_003C R/W PTM2 Local Address
PCICFGADR FEC0_0000 R/W PCI Configuration Address Register
PCICFGDATA FEC0_0004 R/W PCI Configuration Data Register
Table 107. PCI Configuration Register Offsets
PCI Config Register Offset R/W Description
PCIVENDID 01 - 00 R/W Vendor ID
PCIDEVID 03 - 02 R Device ID
PCICMD 05 - 04 R/W Command Register
PCISTATUS 07 -06 R/W Status Register
PCIREVID 08 R Revision ID
PCIINTCLS 09 R/W Interface Class
PCISUBCLS 0A R/W Sub-Class Code
PCIBASECC 0B R/W Base Class Code
PCICACHELS 0C R Cache Line Size
PCILATTIM 0D R/W Latency Timer
PCIHDTYPE 0E R Header Type
PCIBIST 0F R Built In Self Test Control
PCIBAR0 10 R Unused BAR 0
PCIPTM1BAR 14 R/W PTM 1 BAR
PCIPTM2BAR 18 R/W PTM 2 BAR
Reserved 1C - 27 Unused BARs
Reserved 28 - 2B Unused Cardbus
PCISUBSYSID 2C R/W PCI Subsystem ID
PCISUBSYSVENDID 2E R/W PCI Subsystem Vendor ID
Reserved 30 - 3B Unused or Reserved
PCIINTLN 3C R/W Interrupt Line
PCIINTPN 3D R Interrupt Pin
PCIMINGNT 3E R Minimum Grant
PCIMAXLTNCY 3F R Maximum Latency
Table 106. PCI Interface Registers (Continued)
Register Address R/W Description