IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 8-13
0x1 - one byte transferred
0x2 - two bytes transferred
0x3 three bytes transferred
0x4 - four bytes transferred
0x5 through 0x7 - reserved for future use
Bits 0:3 are cleared when a new slave operation starts on the IIC bus, the program clears the slave read
needs service bit in the extended control and slave status register, or the program clears the slave write
needs service bit in the extended control and slave status register.
8.4.12 Extended Control and Slave Status Register
The IIC interface can be reset via software through the IIC reset bit in the CPRRESET register (see Sec-
tion 6.5.2, “Peripheral Reset Control Register (CPRRESET)” ) and the soft reset (bit 7) of the Extended
Control and Slave Status register. Bits 0:6 of this register are cleared by either reset. Bits 0:3 are also
cleared to a logic 0 when written with a logic 1. Bit 7 is cleared by writing a logic 0 to bit 7 or by asserting
the IIC reset bit the CPRRESET register. Note that when setting the IIC reset bit in the CPRRESET regis-
ter, the IIC interface is held in a reset state until the IIC reset bit is cleared.
Software has complete control of the soft reset function when bit 7 is used. The IIC interface will be held in
the reset state as long as this bit is set to a logic 1. Software must write a logic 0 to this bit to deactivate the
reset. Proper operation of the reset requires that bit 7 remain set to a logic 1 for a minimum of eight system
clock periods. Subsequent to setting bit 7 to a logic 0, a minimum of eight system clock periods must occur
before any other registers in the IIC interface are programmed.
Care must be used when changing the setting of bit 6, enable pulsed IRQ. If this bit is changed from a logic
1 to a logic 0 while an interrupt is active, the IIC interrupt signal to the CPC700’s interrupt controller will go
active. If this bit is changed from a logic 0 to a logic 1 while an interrupt is active, then the IIC interrupt sig-
nal to the CPC700’s interrupt controller will go inactive.
After a slave data buffer is read or written, time must be allowed to pass for bits 4 and 5 to be updated. The
actual amount of time is dependent upon the size of the access to or from the buffer. For double-byte
accesses, the status will be readable on the third system clock period after the transfer. For byte accesses,
the status will be readable on the second system clock period after the transfer.
If the slave write needs service, the slave write complete, the slave read needs service, or the slave read
complete bit is set and the enable hold SCL is programmed to a logic 0, then an interlock condition is in
effect such that all new slave operations will not be accepted over the IIC bus. A not acknowledge will be
issued until the slave needs service bits and the slave complete bits are cleared to a logic 0.
Table 93. Transfer Count Register
Register ‘FF6X_000E’ - Transfer Count
bit 0 reserved
bit 1 Slave Transfer Count bit 0 (MSB)
bit 2 Slave Transfer Count bit 1
bit 3 Slave Transfer Count bit 2 (LSB)
bit 4 reserved
bit 5 Master Transfer Count bit 0 (MSB)
bit 6 Master Transfer Count bit 1
bit 7 Master Transfer Count bit 2 (LSB)