IBM CPC700, User Manual

Page: 120 / 268

4-48 Memory Controller
4.9.2 SDRAM Specific Configuration Registers
4.9.2.1 SDTR1 - SDRAM Timing Register 1
Address Offset: x80
Width:
32
Reset Value: x0004_9C0A
Access: Read/Write
This register contains SDRAM related timing parameters.
Bit Name Reset
Value Description
0:11 MBxEA 0s Memory Bank x ending address.
Bit 0 corresponds to CPU A0, bit 11 corresponds to CPU A11.
12:31 0s Reserved
Bit
Name Reset
Value Description
0:6 0s Reserved
7:8 SD_CASL 00 SDRAM CAS_ latency:
00 - 2 CLK
01 - 3 CLK
1x - Reserved
This setting is used during the SDRAM Mode Set Command.
9 SD_APGE 0 SDRAM Auto-Precharge enable.
0 - Auto Precharge Disabled
1 - Auto Precharge Enabled
When enabled, all SDRAM accesses will be performed as Read
w/Auto-Precharge or Write w/Auto-Precharge. SD_RTP and
SD_WTP should be programmed to indicate the respective
number of clock cycles from the Read/Write command to Auto-
Precharge begin.
10 SD_RRD 0 SDRAM module minimum Bank-to-Bank Delay.
0 - 2 CLK
1 - Reserved