IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 14-3
14.1.3 PCI Interface Registers
The following table lists the directly accessible PCI Interface registers. See Section 5.9.1, “PCI Interface
Local Configuration Register Descriptions” for detailed register information.
MB0EA 58 R/W Memory Bank 0 Ending Address
MB1EA 5C R/W Memory Bank 1 Ending Address
MB2EA 60 R/W Memory Bank 2 Ending Address
MB3EA 64 R/W Memory Bank 3 Ending Address
MB4EA 68 R/W Memory Bank 4 Ending Address
SDTR1 80 R/W SDRAM Timing register 1
RBW 88 R/W ROM Bank Width
FWEN 90 R/W Flash Write Enable
ECCCF 94 R/W ECC Configuration
ECCERR 98 R/W ECC Error
RPB0P E0 R/W ROM / Peripheral Bank 0 Parameters
RPB1P E4 R/W ROM / Peripheral Bank 1 Parameters
RPB2P E8 R/W ROM / Peripheral Bank 2 Parameters
RPB3P EC R/W ROM / Peripheral Bank 3 Parameters
RPB4P F0 R/W ROM / Peripheral Bank 4 Parameters
Table 106. PCI Interface Registers
Register Address R/W Description
PMM0LA FF40_0000 R/W PMM 0 Local Address
PMM0MA FF40_0004 R/W PMM 0 Mask/Attribute
PMM0PCILA FF40_0008 R/W PMM 0 PCI Low Address
PMM0PCIHA FF40_000C R/W PMM 0 PCI High Address
PMM1LA FF40_0010 R/W PMM 1 Local Address
PMM1MA FF40_0014 R/W PMM 1 Mask/Attribute
PMM1PCILA FF40_0018 R/W PMM 1 PCI Low Address
PMM1PCIHA FF40_001C R/W PMM 1 PCI High Address
PMM2LA FF40_0020 R/W PMM 2 Local Address
PMM2MA FF40_0024 R/W PMM 2 Mask/Attribute
PMM2PCILA FF40_0028 R/W PMM 2 PCI Low Address
PMM2PCIHA FF40_002C R/W PMM 2 PCI High Address
Table 105. Offsets for Memory Controller Registers (Continued)
Register Offset R/W Description