IBM CPC700, User Manual

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CPC700 User’s Manual—Preliminary 4-29
4.6 ROM/Peripheral Controller
The memory controller provides support for 8, 16, 32, and 64 bit burst and non-burst ROM-like devices
(EPROM, SRAM) attached to the memory bus. In addition, external peripheral devices which have an inter-
face similar to that of an SRAM may be attached to the ROM bus. A “Ready” input pin is provided to allow
device pacing of peripherals.
ROM address, control, and data are shared with the DRAM interface with additional signals provided to con-
trol an external latch for the ROM address. This external latch is required to allow for the ROM and DRAM
interface to share the memory address bus.
4.6.1 Peripheral Bus Behavior
For any peripheral (non-SDRAM) access, regardless of peripheral device width, the CPC700 internally
conducts a 64 bit transaction with all byte enables asserted. If the transaction is a write, only one external
access is seen on the peripheral bus. That access is a write of all bytes of the programmed device width. If
the transaction is a read, enough external transactions will take place to build a 64-bit internal transaction.
That means 8 accesses in a region programmed as byte wide, 4 accesses in region programmed as 16 bit,
2 accesses in a region programmed as word wide, and 1 access in a doubleword area. In a region used for
hardware control registers, the user must be aware of this behavior, since some hardware registers are
volatile under read operations.
Note the following about the usage of the peripheral address bus and about chip select addresses:
• Bit 0 of the peripheral address bus is the low order bit for the device width programmed for the active
CPC700 bank. If the width is programmed as byte, then the address bus carries byte addresses. If the
width is programmed as doubleword (8 byte), then the address bus carries doubleword addresses
(bit 0, the LSb of the peripheral bus, references a doubleword, and no byte address exists on the bus).
• Chip select signals are generated when the CPC700 detects accesses to addresses bracketed by the
contents of a memory bank starting/ending address register pair (MBxSA/MBxEA). The comparison of
address to register content occurs internal to the CPC700 based on the actual byte address. The
comparison does not involve the external peripheral bus, and so does not change with programmed
device width.
It may be desirable to access a byte-wide peripheral as a doubleword device to avoid the 8 single byte
accesses that would occur if a single byte read was done with the peripheral configured as a byte device.
These 8 accesses have the potential of destroying data in hardware registers that are volatile upon read
operations. By configuring the byte-wide peripheral as a doubleword device (where a single doubleword
access is performed as opposed to 8 accesses) this potential problem can be avoided. To access a byte-
wide peripheral as a doubleword device, the addresses used to access the bank must be adjusted properly
by the programmer, as follows:
• Since the address space for the peripheral is eight times larger when in doubleword mode than when
in byte mode, the peripheral’s memory bank starting address register (MBxSA) and ending address
register (MBxEA) may need to be modified to define a larger address space.
• Since the peripheral’s addressable bytes are on doubleword boundaries when in doubleword mode (as
opposed to byte boundaries when in byte mode), the offset from the contents of the starting address
register must be multiplied by 8 from the natural byte-offset. For a byte-wide device in doubleword
mode, meaningful data exists only at the bytes on doubleword boundaries; the intervening seven
bytes do not access any data.
If a region of the address space is going to be used for instruction fetching, it is mandatory that the
programmed device width equals the actual device width. Assume an NVRAM device is wired as a byte
device. If programmed as a byte device, instruction fetching may be done from NVRAM. Note that a one-
byte data read (“lbz” instruction) will result in 8 reads occurring on the bus, which may be undesirable. If