IBM CPC700, User Manual

Page: 253 / 268

CPC700 User’s Manual—Preliminary 14-1
Chapter 14. Register Summary
14.1 CPC700 Registers
Registers within the CPC700 are located according to the following tables. Detailed descriptions may be
found in the individual chapters.
14.1.1 Processor Interface Registers
Processor interface registers are accessed through an indirect method employing a configuration address
register, PIFCFGADR, and a configuration data register, PIFCFGDATA. To access one of the processor
interface registers, write the appropriate index to register PIFCFGADR, then read the data from or write the
data to register PIFCFGDATA. All configuration accesses from the processor must be 4 Byte aligned, oth-
erwise an error will be generated and the cycle not performed. The table below lists the indirect address
and data registers in the processor interface address map.
The following table lists the offsets for the various configuration registers located within the processor inter-
face. See Section 3.16, “Processor Interface Register Description” for detailed register information.
Table 102. Processor Interface Register Addressing
Register Address R/W Description
PIFCFGADR FF50_0000 R/W Processor Interface Configuration Address Register
PIFCFGDATA FF50_0004 R/W Processor Interface Configuration Data Register
Table 103. Offsets for Processor Interface Registers
Register Offset R/W Description
PRIFOPT1 00 R/W Processor Interface Options 1
ERRDET1 04 R/W Error Detection 1
ERREN1 08 R/W Error Detection Enable 1
CPUERAD 0C R Processor Error Address
CPUERAT 10 R Processor Error Attributes
Reserved 14
PLBMIFOPT 18 R/W Processor-PLB Master Interface Options
PLBMTLSA1 20 R/W Processor-PLB Bank 1 Translation Start Address
PLBMTLEA1 24 R/W Processor-PLB Bank 1 Translation End Address
PLBMTLSA2 28 R/W Processor-PLB Bank 2 Translation Start Address
PLBMTLEA2 2C R/W Processor-PLB Bank 2 Translation End Address
PLBMTLSA3 30 R/W Processor-PLB Bank 3 Translation Start Address
PLBMTLEA3 34 R/W Processor-PLB Bank 3 Translation End Address
PLBSNSSA0 38 R/W No Snoop Starting Address
PLBSNSEA0 3C R/W No Snoop Ending Address
BESR 40 R/W PLB Bus Error Syndrome Register