IBM CPC700, User Manual

Page: 102 / 268

4-30 Memory Controller
programmed as a doubleword device, any byte may be accessed with only one read occurring on the bus,
but valid data exists only at the bytes on doubleword boundaries. Thus, when programmed as doubleword,
instruction fetching cannot occur from the NVRAM.
4.6.2 Reads
The internal memory data interface to the ROM controller is 64 bits wide independent of the ROM device
width. As such, the memory controller will generate single beat read requests with all byte enables asserted.
A beat consists of a 1-8 byte data transfer as defined by the byte enable assertion. The response to these
requests depends on the ROM device width:
All single beat reads from memory will return a full 8-byte doubleword regardless of the device data bus
width. For example, in the case that an 8-bit ROM/peripheral is attached, a single byte read from the local
processor will result in 8 sequential single-byte reads from the ROM device (starting on the doubleword
boundary) and the entire assembled doubleword will be returned to the processor. Care must be taken when
attaching peripherals in which extra reads may have unwanted side effects (i.e. FIFOs).
4.6.3 Writes
The ROM/Peripheral interface only supports device wide, aligned, single beat write cycles.
All other combinations of device width and write size/alignment are not supported and will generate a mem-
ory select error and a write error. Both errors will be logged if error logging is enabled.
Table 27. ROM Response to Memory Controller Read Cycles
Memory Read Request Response
Single Beat Single Burst CPU Read Return 8 bytes
2 Beat (PCI only)
(Wrap addr inc.) 16 sequential bytes returned, wrapping at end of
16 byte boundary
4 Beat (Burst from PCI)
(Wrap addr inc.) 32 sequential bytes returned, wrapping at end of
32 byte boundary
Table 28. ROM Response to Memory Controller Write Cycles
Memory Write Request Required data size
8-bit 1 byte
16-bit 2 bytes and aligned
32-bit 4 bytes and aligned
64-bit 8 bytes and aligned